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| | * | ParserYRabbit2021-07-051-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | Merge branch 'master' into io_portYRabbit2021-07-031-2/+13
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| | * | | Fix parser. Comments and IO_PORTYRabbit2021-07-031-11/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | | SyntaxYRabbit2021-07-021-3/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * | | Add IO_PORT parsingYRabbit2021-07-021-14/+27
| | | | | | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | | | Merge pull request #756 from acomodi/fix-clustering-runtimegatecat2021-07-085-7/+69
| |\ \ \ \ | | | | | | | | | | | | interchange: reduce run-time to check dedicated interconnect
| | * | | | interchange: bump python-interchange versionAlessandro Comodi2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| | * | | | interchange: update chipdb versionAlessandro Comodi2021-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| | * | | | interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-084-5/+67
| |/ / / / | | | | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* / / / / ice40: Fix order of values in errorgatecat2021-07-101-1/+1
|/ / / / | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | / clangformatgatecat2021-07-081-2/+1
| |_|/ |/| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #751 from trabucayre/gw1ns-2gatecat2021-07-063-7/+8
|\ \ \ | | | | | | | | add support for GW1NS-2 family
| * | | .cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9Gwenhael Goavec-Merou2021-07-061-1/+1
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| * | | add support for GW1NS-2 familyGwenhael Goavec-Merou2021-07-062-6/+7
| | |/ | |/| | | | | | | Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
* | | Merge pull request #754 from YosysHQ/gatecat/ecp5-dcsgatecat2021-07-064-11/+55
|\ \ \ | | | | | | | | ecp5: Add DCSC support
| * | | ecp5: Add DCSC supportgatecat2021-07-064-11/+55
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #752 from YosysHQ/gatecat/du-mem-errorgatecat2021-07-061-1/+2
|\ \ \ | | | | | | | | design_utils: Fix memory error
| * | | design_utils: Fix memory errorgatecat2021-07-061-1/+2
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #750 from YosysHQ/gatecat/io-improvegatecat2021-07-0610-59/+136
|\ \ \ | |/ / |/| | IO improvements for OBUFTDS
| * | interchange: Allow pseudo pip wires to overlap with bound site wires on the ↵gatecat2021-07-063-17/+13
| | | | | | | | | | | | | | | | | | same net Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Dump pre-bound routes when routing fails in debug modegatecat2021-07-061-1/+11
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Improve search for PAD-attached belsgatecat2021-07-062-41/+32
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: tests: add obuftds testAlessandro Comodi2021-07-066-0/+80
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #748 from acomodi/fix-phys-net-writinggatecat2021-07-021-2/+13
|\ \ | |/ |/| interchange: phys: skip only nets writing on disconnected out ports
| * interchange: phys: skip only nets writing on disconnected out portsAlessandro Comodi2021-07-021-2/+13
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #747 from cr1901/machxo2gatecat2021-07-019-13/+140
|\ | | | | MachXO2 Checkpoint 1
| * machxo2: Fix packing for directly-connected DFFs.William D. Jones2021-07-013-9/+28
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| * machxo2: Add VHDL primitives, demo, and script.William D. Jones2021-07-014-0/+81
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| * machxo2: Add a special case for pips whose config bits are in multipleWilliam D. Jones2021-07-011-0/+12
| | | | | | | | tiles.
| * machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.William D. Jones2021-07-011-2/+17
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| * machxo2: Set Pip and Wire delays to reasonable fake values mirroringWilliam D. Jones2021-07-011-2/+2
| | | | | | | | estimateDelay.
* | Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-constgatecat2021-07-011-5/+9
|\ \ | | | | | | interchange: Handle canInvert PIPs when processing preferred constants
| * | interchange: Handle canInvert PIPs when processing preferred constantsgatecat2021-07-011-5/+9
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #745 from YosysHQ/gatecat/ic-node-sourcegatecat2021-07-011-0/+5
|\ \ | |/ |/| interchange: Handle case where routing source is a node
| * interchange: Handle case where routing source is a nodegatecat2021-07-011-0/+5
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-07-011-1/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
|\ | | | | interchange: Fix handling of constants in macros
| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #743 from YosysHQ/gatecat/site-rsv-portsgatecat2021-07-015-0/+69
|\ \ | | | | | | interchange: Reserve site ports only reachable from dedicated routing
| * | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-015-0/+69
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-netsgatecat2021-07-011-1/+12
|\ \ | |/ |/| interchange: phys: do not output nets which have no users
| * interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #741 from acomodi/fix-ded-intercgatecat2021-06-301-8/+14
|\ | | | | interchange: fix dedicated interconnect exploration
| * interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #739 from YosysHQ/gatecat/usp-io-macrogatecat2021-06-305-1/+91
|\ | | | | interchange: Place entire IO macro based on routeability
| * interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #738 from YosysHQ/json_load_reinitgatecat2021-06-303-11/+11
|\ \ | | | | | | Preserve ArchArgs and reinit Context when applicable in GUI, fixes #737
| * | Preserve ArchArgs and reinit Context when applicable in GUIMiodrag Milanovic2021-06-303-11/+11
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