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Age
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|
*
mistral: Trim SDATA if SLOAD is low
gatecat
2021-05-15
1
-0
/
+9
|
*
mistral: FF&CLKBUF fixes, part 1
gatecat
2021-05-15
2
-1
/
+10
|
*
mistral: First pass at FF and CLKBUF bitgen
gatecat
2021-05-15
2
-18
/
+115
|
*
mistral: Account for TD input count limit
gatecat
2021-05-15
4
-9
/
+128
|
*
msitral: Fix pip iterator Python bindings
gatecat
2021-05-15
1
-2
/
+2
|
*
mistral: Implement PIP locations, too
gatecat
2021-05-15
1
-1
/
+1
|
*
mistral: Implement bounding boxes for router2
gatecat
2021-05-15
2
-1
/
+15
|
*
mistral: Debugging carry chain issues
gatecat
2021-05-15
2
-13
/
+34
|
*
mistral: Adding FF control set reservation
gatecat
2021-05-15
3
-58
/
+148
|
*
mistral: Carry fixes
gatecat
2021-05-15
2
-3
/
+16
|
*
mistral: Carry debugging
gatecat
2021-05-15
3
-41
/
+11
|
*
mistral: Write arith mode to bitstream (not yet functional)
gatecat
2021-05-15
2
-2
/
+18
|
*
mistral: First pass at carry packing
gatecat
2021-05-15
4
-8
/
+82
|
*
mistral: FF validity checking fixes
gatecat
2021-05-15
1
-7
/
+13
|
*
mistral: Fix constant trimming
gatecat
2021-05-15
2
-1
/
+2
|
*
mistral: Write LUT inits
gatecat
2021-05-15
2
-1
/
+72
|
*
mistral: Add some IO configuration
gatecat
2021-05-15
1
-0
/
+30
|
*
mistral: Setting some more boilerplate bits
gatecat
2021-05-15
3
-1
/
+118
|
*
mistral: Add stub RBF generation
gatecat
2021-05-15
4
-9
/
+108
|
*
mistral: Rename clock buffer primitive
gatecat
2021-05-15
2
-2
/
+3
|
*
mistral: Python and GUI stub
gatecat
2021-05-15
6
-0
/
+350
|
*
mistral: Implement some misc. things
gatecat
2021-05-15
4
-10
/
+78
|
*
mistral: Some preps for generating bitstreams
gatecat
2021-05-15
4
-28
/
+131
|
*
mistral: Adding a function for computing ALM LUT masks
gatecat
2021-05-15
2
-0
/
+90
|
*
mistral: Add IO packing
gatecat
2021-05-15
5
-8
/
+135
|
*
mistral: Add a basic QSF parser
gatecat
2021-05-15
4
-1
/
+295
|
*
mistral: Add some packing logic based on nexus
gatecat
2021-05-15
4
-3
/
+202
|
*
mistral: Working on FF validity checking
gatecat
2021-05-15
2
-1
/
+117
|
*
mistral: Add the 'pin style' stuff based on Nexus
gatecat
2021-05-15
2
-0
/
+112
|
*
mistral: Working on ALM input assignment
gatecat
2021-05-15
2
-2
/
+118
|
*
mistral: Add stub pack/place/route functions
gatecat
2021-05-15
5
-5
/
+143
|
*
mistral: Renamed arch from cyclonev
gatecat
2021-05-15
9
-4
/
+4
|
*
cyclonev: Rebase update
gatecat
2021-05-15
1
-1
/
+3
|
*
cyclonev: More validity checking thoughts
gatecat
2021-05-15
5
-7
/
+49
|
*
cyclonev: Add validity check and IO bels
gatecat
2021-05-15
5
-9
/
+92
|
*
cyclonev: First (untested) pass at ALM validity checking
gatecat
2021-05-15
2
-40
/
+135
|
*
cyclonev: More preparations for validity checking
gatecat
2021-05-15
5
-7
/
+159
|
*
cyclonev: Preparations for validity checking
gatecat
2021-05-15
2
-0
/
+37
|
*
cyclonev: Fix some archcheck fails
gatecat
2021-05-15
3
-4
/
+6
|
*
cyclonev: Rework bels
gatecat
2021-05-15
3
-97
/
+76
|
*
cyclonev: Outline LAB structure
gatecat
2021-05-15
4
-4
/
+207
|
*
cyclonev: Outline functions for creating bels/wires/pips
gatecat
2021-05-15
2
-3
/
+104
|
*
archcheck: Use old connectivity check for CycloneV
gatecat
2021-05-15
1
-1
/
+29
|
*
cyclonev: Add routing graph
gatecat
2021-05-15
2
-4
/
+73
|
*
cyclonev: Add names and archcheck fixes
gatecat
2021-05-15
5
-54
/
+138
|
*
cyclonev: Add some range types
gatecat
2021-05-15
1
-7
/
+69
|
*
cyclonev: Add enough stubs that it links
gatecat
2021-05-15
4
-28
/
+147
|
*
cyclonev: Add wire and pip types
gatecat
2021-05-15
2
-12
/
+45
|
*
cyclonev: Add some useful constids
gatecat
2021-05-15
3
-0
/
+76
|
*
cyclonev: Update in line with nextpnr changes
gatecat
2021-05-15
5
-239
/
+128
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