aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | mistral: DATAIN and DATAOUT of GPIO have swappedgatecat2021-12-121-2/+2
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge branch 'master' of github.com:YosysHQ/nextpnrgatecat2021-12-121-0/+3
|\ \
| * \ Merge pull request #865 from yrabbit/ALU-head-at-zerogatecat2021-12-121-0/+3
| |\ \ | | | | | | | | gowin: BUGFIX. Place the ALU head in sliсe 0 only
| | * \ Merge branch 'YosysHQ:master' into ALU-head-at-zeroYRabbit2021-12-123-3/+3
| | |\ \
| | * | | gowin: BUGFIX. Place the ALU head in sliсe 0 onlyYRabbit2021-12-111-0/+3
| | | |/ | | |/| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | / | clangformatgatecat2021-12-122-16/+13
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | / router2: Error instead of hang in case of reservation conflictsgatecat2021-12-121-0/+3
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #866 from YosysHQ/gatecat/mistral-include-toolsgatecat2021-12-113-3/+3
|\ \ | |/ |/| mistral: Add 'tools' dir to include path
| * mistral: Add 'tools' dir to include pathgatecat2021-12-113-3/+3
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #863 from antmicro/pack_lutffgatecat2021-11-242-0/+182
|\ | | | | nexus: LUT and FF clustering
| * Added checking if all FFs added to an existing cluster have matching ↵Maciej Kurc2021-11-231-0/+44
| | | | | | | | | | | | configuration Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed potential issues with carry-chain cluster expansion, added a parameter ↵Maciej Kurc2021-11-222-14/+23
| | | | | | | | | | | | controlling the ratio of FFs that got glued to carry-chain clusters. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added appending FFs to other existing LUT cluster types (carry, widefn)Maciej Kurc2021-11-221-18/+67
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added an option to control LUT and FF packingMaciej Kurc2021-11-222-1/+8
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added clustering free LUTs and FFsMaciej Kurc2021-11-221-0/+73
|/ | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #862 from DX-MON/mastergatecat2021-11-191-6/+4
|\ | | | | common: Improved the random seed initialisation for the context
| * common: Improved the random seed initialisation for the contextdx-mon2021-11-191-6/+4
|/
* Merge pull request #859 from yrabbit/gowin-packagesgatecat2021-11-074-17/+53
|\ | | | | gowin: Add partnumbers and packages to the chipdb
| * gowin: Check the chipdb versionYRabbit2021-11-072-1/+7
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: use latest Apycula releaseYRabbit2021-11-071-1/+1
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into gowin-packagesYRabbit2021-11-062-3/+11
| |\ | |/ |/|
* | Merge pull request #857 from YosysHQ/gatecat/ecp5-ff-iodelgatecat2021-11-052-3/+11
|\ \ | | | | | | ecp5: Fix packing of IOFF with IODELAYs
| * | ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: Use speed from chip base.YRabbit2021-11-053-20/+27
| | | | | | | | | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-043-6/+29
|/ | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #855 from galibert/mastergatecat2021-10-282-4/+3
|\ | | | | mistral: Sync with yet another reorganization
| * mistral: Sync with yet another reorganizationOlivier Galibert2021-10-282-4/+3
|/
* Merge pull request #852 from yrabbit/pr-gowin-alugatecat2021-10-223-6/+226
|\ | | | | gowin: Add ALU support.
| * gowin: Explicitly initialize the y in the clusterYRabbit2021-10-221-0/+5
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add ALU support.YRabbit2021-10-223-6/+221
|/ | | | | | | | - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* interchange: Bump prjoxide versiongatecat2021-10-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #851 from galibert/mastergatecat2021-10-193-13/+14
|\ | | | | mistral: Use the iterators
| * Normalize formattingOlivier Galibert2021-10-192-13/+17
| |
| * mistral: Use the iteratorsOlivier Galibert2021-10-192-12/+9
|/
* Merge pull request #848 from galibert/mastergatecat2021-10-172-1/+2
|\ | | | | mistral: Support the new routes-to-bin intermediate tool generation
| * Sync mistral version in CIOlivier Galibert2021-10-171-1/+1
| |
| * mistral: Support the new routes-to-bin intermediate tool generationOlivier Galibert2021-10-171-0/+1
| |
* | Merge pull request #849 from galibert/cyclonev-oscillatorgatecat2021-10-174-3/+15
|\ \ | |/ |/| mistral: Add internal oscillator support
| * mistral: Add internal oscillator supportOlivier Galibert2021-10-174-3/+15
|/
* Merge pull request #847 from galibert/mastergatecat2021-10-154-0/+17
|\ | | | | mistral: Add support for cyclonev_hps_interface_mpu_general_purpose
| * cyclonev_hps_interface_mpu_general_purpose: Use a id_ identifierOlivier Galibert2021-10-152-1/+3
| |
| * mistral: Add support for cyclonev_hps_interface_mpu_general_purposeOlivier Galibert2021-10-143-0/+15
|/
* Merge pull request #845 from YosysHQ/gatecat/mlab-cluster-fixgatecat2021-10-112-2/+9
|\ | | | | mistral: Fix MLAB clustering
| * mistral: Fix MLAB clusteringgatecat2021-10-112-2/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-10-112-29/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timinggatecat2021-10-113-21/+256
|\ | | | | mistral: very basic timing info
| * mistral: very basic timing infoLofty2021-10-104-22/+257
| |
* | Merge pull request #844 from pepijndevos/patch-2gatecat2021-10-101-2/+2
|\ \ | | | | | | Gowin: more clearly mark dummy pips
| * | Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
|/ /
* | Merge pull request #842 from yrabbit/delaysgatecat2021-10-093-12/+40
|\ \ | | | | | | gowin: Replace the zero delays with reasonable values.
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 04:21:57 +0000