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* Move TileType array to ice40 chipdb blobClifford Wolf2018-06-172-7/+14
* Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-173-17/+23
* Move IerenInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-12/+11
* Move TileInfoPOD to chipdb blobClifford Wolf2018-06-172-8/+16
* Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-172-15/+25
* Move PipInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-6/+28
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-1722-84/+387
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| * place_sa: Make placement independant of unordered_map orderingDavid Shah2018-06-171-4/+8
| * General reformattingDavid Shah2018-06-174-4/+3
| * frontend/json: Look up netnames properly instead of using numberDavid Shah2018-06-171-7/+43
| * ice40: Add symbol output to bitstream generationDavid Shah2018-06-171-6/+8
| * Updating copyrightsDavid Shah2018-06-1717-7/+21
| * Improving the placer outputDavid Shah2018-06-176-15/+42
| * place_sa: Ignore Bels locked by manual placement for SA swapsDavid Shah2018-06-171-2/+8
| * Add 'get or default' functionsDavid Shah2018-06-172-3/+67
| * place_sa: Run a validity check at the end of placementDavid Shah2018-06-171-0/+9
| * ice40: Fixing buildDavid Shah2018-06-172-2/+2
| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-162-1/+1
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| | * Renamed place.h to place_sa.h in place_sa.ccZipCPU2018-06-161-1/+1
| | * Changed place.h place_sa.hZipCPU2018-06-161-0/+0
| * | place: Fix placer validity checksDavid Shah2018-06-163-6/+33
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| * Renamed placer to Simulated-Annealing placerZipCPU2018-06-161-0/+0
| * ice40: Proper global promotionDavid Shah2018-06-164-24/+83
| * ice40: Promote reset signalDavid Shah2018-06-165-36/+89
| * Tweaking placer and routerDavid Shah2018-06-162-4/+7
* | Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-173-39/+61
* | Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-174-84/+145
* | Progress with chipdb refactoringClifford Wolf2018-06-164-23/+39
* | Progress with chipdb refactoringClifford Wolf2018-06-163-42/+37
* | Progress with chipdb refactoringClifford Wolf2018-06-163-33/+175
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* Update placer for new Chip APIClifford Wolf2018-06-161-6/+6
* Update clangformatClifford Wolf2018-06-161-1/+1
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-1612-76/+440
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| * router: Fixing loop issueDavid Shah2018-06-161-0/+1
| * Merge branch 'simann'David Shah2018-06-1611-76/+439
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| | * ice40: Fix RAM config in packerDavid Shah2018-06-161-1/+2
| | * ice40: Fix BRAM initialisationDavid Shah2018-06-162-4/+4
| | * place: Tidying up the SA placerDavid Shah2018-06-163-109/+37
| | * ice40: Include RAM init data in bitstreamDavid Shah2018-06-161-0/+40
| | * ice40: Fix bitstream generation when parameters are unspecifiedDavid Shah2018-06-161-13/+23
| | * place: Reformat placerDavid Shah2018-06-161-49/+46
| | * ice40: Bitstream generation for RAMDavid Shah2018-06-161-1/+36
| | * ice40: Only place IO at valid pinsDavid Shah2018-06-163-3/+14
| | * Improve placement heuristicDavid Shah2018-06-161-2/+1
| | * Fix router for routing to the same dest wire twiceClifford Wolf2018-06-161-21/+16
| | * Remove dead codeDavid Shah2018-06-161-8/+0
| | * Improving SA placer performanceDavid Shah2018-06-161-21/+50
| | * Very slow SA placer based on arachne-pnrDavid Shah2018-06-161-60/+241
| | * Create all without ui file, enables more controlMiodrag Milanovic2018-06-164-173/+93
| | * Propagate signalsMiodrag Milanovic2018-06-164-2/+13
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