iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	generic: Don't generate Vcc if not needed	gatecat	2021-02-17	2	-5/+7
*	Merge pull request #586 from litghost/add_cell_bel_mapping_only	gatecat	2021-02-17	2	-13/+274
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\| *	Require `--package` when arch BBA contains multiple packages.	Keith Rothman	2021-02-16	1	-3/+11
\| *	[FPGA Interchange] Add Cell -> BEL Pin maps.	Keith Rothman	2021-02-16	2	-13/+266
* \|	Merge pull request #585 from YosysHQ/gatecat/remove-ivbfc	gatecat	2021-02-17	24	-287/+170
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\| *	Remove isValidBelForCell	gatecat	2021-02-16	24	-287/+170
* \|	Bump test submodule	gatecat	2021-02-16	1	-0/+0
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*	Merge pull request #583 from litghost/add_fpga_interchange_front_and_backend	gatecat	2021-02-16	11	-7/+909
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\| *	Pull in fix for out of source builds.	Keith Rothman	2021-02-15	1	-0/+0
\| *	Move CMake logic into fpga-interchange-schema.	Keith Rothman	2021-02-15	2	-13/+1
\| *	Small fixes from review.	Keith Rothman	2021-02-15	2	-2/+2
\| *	Add libcapnp-dev for FPGA interchange compilation support.	Keith Rothman	2021-02-15	1	-1/+2
\| *	Add FPGA interchange frontend and backend.	Keith Rothman	2021-02-15	7	-5/+915
\| *	Add interchange schema 3rdparty.	Keith Rothman	2021-02-15	2	-0/+3
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*	Merge pull request #584 from YosysHQ/gatecat/generic-belpin	gatecat	2021-02-15	7	-5/+40
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\| *	generic: Update docs	gatecat	2021-02-15	1	-2/+10
\| *	generic: Add bel pin mapping test	gatecat	2021-02-15	2	-0/+1
\| *	generic: Add APIs for controlling cell->bel pin mapping	gatecat	2021-02-15	4	-3/+29
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*	Merge pull request #578 from YosysHQ/machxo2-rebase	gatecat	2021-02-15	38	-3/+4511
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\| *	ci: Bump prjtrellis version	gatecat	2021-02-12	1	-1/+1
\| *	Fix bad rebase	gatecat	2021-02-12	1	-2/+1
\| *	machxo2: Misc tidying up	gatecat	2021-02-12	2	-8/+4
\| *	machxo2: Python bindings and stub GUI	gatecat	2021-02-12	9	-6/+346
\| *	machxo2: Use snake_case for non-ArchAPI functions	gatecat	2021-02-12	4	-63/+63
\| *	machxo2: Use IdStringLists in earnest	gatecat	2021-02-12	2	-76/+70
\| *	machxo2: Update with Arch API changes	gatecat	2021-02-12	9	-468/+119
\| *	machxo2: Prepare README.md for first PR.	William D. Jones	2021-02-12	1	-4/+36
\| *	machxo2: Add prefix parameter to simtest.sh. Remove show command from	William D. Jones	2021-02-12	3	-40/+43
\| *	machxo2: Add prefix parameter to simple.sh. Update README.md.	William D. Jones	2021-02-12	2	-14/+14
\| *	machxo2: Fill in more about mitertest.sh in README.md and clean up a bit.	William D. Jones	2021-02-12	1	-4/+27
\| *	machxo2: Add two new examples: blinky_ext and aforementioned UART.	William D. Jones	2021-02-12	3	-0/+238
\| *	machxo2: auto-top does not work for smt miter either.	William D. Jones	2021-02-12	1	-1/+1
\| *	machxo2: Fix unhelpful comment in mitertest.sh.	William D. Jones	2021-02-12	1	-1/+0
\| *	machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Rem...	William D. Jones	2021-02-12	1	-3/+7
\| *	machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules ...	William D. Jones	2021-02-12	3	-37/+37
\| *	machxo2: Add prefix paramter to demo.sh.	William D. Jones	2021-02-12	4	-22/+37
\| *	Add demo with RGB LED	mtnrbq	2021-02-12	2	-0/+43
\| *	machxo2: Fix packing when FF is driven by a constant; UART test core working ...	William D. Jones	2021-02-12	2	-1/+3
\| *	machxo2: Add packing logic to handle FFs fed with constant value; UART test c...	William D. Jones	2021-02-12	3	-5/+39
\| *	machxo2: Add additional packing phase to pack remaining FFs.	William D. Jones	2021-02-12	1	-0/+38
\| *	machxo2: Don't write out config bits for cells without location info.	William D. Jones	2021-02-12	1	-1/+2
\| *	machxo2: Special-case left and right I/O wire names in ASCII generation.	William D. Jones	2021-02-12	1	-1/+35
\| *	machxo2: Add quickstart README.md.	William D. Jones	2021-02-12	1	-0/+73
\| *	machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now).	William D. Jones	2021-02-12	1	-0/+3
\| *	machxo2: Fix REGMODE identifier (per slice, not per-FF).	William D. Jones	2021-02-12	2	-5/+2
\| *	machxo2: Add demo.sh TinyFPGA Ax example.	William D. Jones	2021-02-12	4	-1/+50
\| *	machxo2: clang format.	William D. Jones	2021-02-12	4	-29/+34
\| *	machxo2: Fix reversed interpretation of REG_SD config bits.	William D. Jones	2021-02-12	1	-6/+0
\| *	machxo2: Add bitstream generation for OSCH.	William D. Jones	2021-02-12	1	-0/+4
\| *	machxo2: Add basic bitstream generation for PIC tiles and I/O.	William D. Jones	2021-02-12	1	-0/+26