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* router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
* router1: Support for multiple bel pins per cell pingatecat2021-02-101-62/+78
* Start making use of getBelPinsForCellPin APIgatecat2021-02-106-38/+84
* Add getBelPinsForCellPin to Arch APIgatecat2021-02-107-0/+26
* Remove the unused CellInfo::pins fieldgatecat2021-02-104-37/+0
* Merge pull request #573 from YosysHQ/gatecat/basearchrangesgatecat2021-02-095-49/+25
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| * Add BaseArchRanges for default ArchRanges typesgatecat2021-02-095-49/+25
* | Add nextpnr-gowin binary to gitignoregatecat2021-02-091-0/+1
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* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-0820-1145/+1334
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| * Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
| * Update docs with API changesD. Shah2021-02-081-21/+160
| * interchange: Base on ArchAPID. Shah2021-02-082-106/+135
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-086-147/+153
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-057-11/+27
| * gowin: Switch to BaseArchD. Shah2021-02-052-150/+107
| * generic: Base upon ArchAPID. Shah2021-02-051-102/+132
| * nexus: Switch to BaseArchD. Shah2021-02-055-301/+103
| * ice40: Switch to BaseArchD. Shah2021-02-055-182/+115
| * Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-053-7/+7
| * Add default implementation of bel bucket functionsD. Shah2021-02-055-88/+94
| * Add default implementation of some range-returning functionsD. Shah2021-02-052-17/+27
| * Add a few more functions to ArchBaseD. Shah2021-02-052-11/+18
| * ecp5: Use common wire/pip bindingD. Shah2021-02-052-83/+7
| * Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
| * nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
| * nextpnr: Use templates to specify range typesD. Shah2021-02-052-18/+67
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-052-84/+176
* | Update prjoxide URLD. Shah2021-02-082-4/+4
* | Merge pull request #572 from YosysHQ/dave/more-ssizeDavid Shah2021-02-084-23/+23
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| * Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-084-23/+23
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* Merge pull request #567 from litghost/initial_fpga_interchangeDavid Shah2021-02-0515-2/+2582
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| * Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-053-27/+29
| * Move all string data into BBA file.Keith Rothman2021-02-055-48901/+16
| * Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-042-97/+67
| * Update APIs to conform to style guide.Keith Rothman2021-02-045-67/+48939
| * Remove unused method getReservedWireNet.Keith Rothman2021-02-041-7/+0
| * Update copywrite headers.Keith Rothman2021-02-048-4/+12
| * Correct some typos.Keith Rothman2021-02-041-4/+4
| * Fix warnings with signed/unsigned.Keith Rothman2021-02-041-1/+1
| * Fix fpga_interchange/README.md duplicate patch statement.Keith Rothman2021-02-041-8/+0
| * Fix URLs in Markdown.Keith Rothman2021-02-041-2/+2
| * Add empty constids.inc for build.Keith Rothman2021-02-041-0/+0
| * Run "make clangformat".Keith Rothman2021-02-044-148/+100
| * Add README about initial state of FPGA interchange implementation.Keith Rothman2021-02-041-0/+170
| * Update FPGA interchange to use IdStringList.Keith Rothman2021-02-042-132/+137
| * Add initial GUI files.Keith Rothman2021-02-044-0/+96
| * Start adding data for placement constraint solving.Keith Rothman2021-02-042-50/+43
| * Debug BEL bucket data.Keith Rothman2021-02-041-11/+14
| * Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-045-0/+247
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