Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | ecp5: Use a vector rather than dict | Matt Johnston | 2021-12-12 | 3 | -14/+106 |
| | | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout | ||||
* | Merge pull request #863 from antmicro/pack_lutff | gatecat | 2021-11-24 | 2 | -0/+182 |
|\ | | | | | nexus: LUT and FF clustering | ||||
| * | Added checking if all FFs added to an existing cluster have matching ↵ | Maciej Kurc | 2021-11-23 | 1 | -0/+44 |
| | | | | | | | | | | | | configuration Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Fixed potential issues with carry-chain cluster expansion, added a parameter ↵ | Maciej Kurc | 2021-11-22 | 2 | -14/+23 |
| | | | | | | | | | | | | controlling the ratio of FFs that got glued to carry-chain clusters. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added appending FFs to other existing LUT cluster types (carry, widefn) | Maciej Kurc | 2021-11-22 | 1 | -18/+67 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added an option to control LUT and FF packing | Maciej Kurc | 2021-11-22 | 2 | -1/+8 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added clustering free LUTs and FFs | Maciej Kurc | 2021-11-22 | 1 | -0/+73 |
|/ | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Merge pull request #862 from DX-MON/master | gatecat | 2021-11-19 | 1 | -6/+4 |
|\ | | | | | common: Improved the random seed initialisation for the context | ||||
| * | common: Improved the random seed initialisation for the context | dx-mon | 2021-11-19 | 1 | -6/+4 |
|/ | |||||
* | Merge pull request #859 from yrabbit/gowin-packages | gatecat | 2021-11-07 | 4 | -17/+53 |
|\ | | | | | gowin: Add partnumbers and packages to the chipdb | ||||
| * | gowin: Check the chipdb version | YRabbit | 2021-11-07 | 2 | -1/+7 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: use latest Apycula release | YRabbit | 2021-11-07 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | Merge branch 'master' into gowin-packages | YRabbit | 2021-11-06 | 2 | -3/+11 |
| |\ | |/ |/| | |||||
* | | Merge pull request #857 from YosysHQ/gatecat/ecp5-ff-iodel | gatecat | 2021-11-05 | 2 | -3/+11 |
|\ \ | | | | | | | ecp5: Fix packing of IOFF with IODELAYs | ||||
| * | | ecp5: Fix packing of IOFF with IODELAYs | gatecat | 2021-11-05 | 2 | -3/+11 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | gowin: Use speed from chip base. | YRabbit | 2021-11-05 | 3 | -20/+27 |
| | | | | | | | | | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: Add partnumbers and packages to the chipdb | YRabbit | 2021-11-04 | 3 | -6/+29 |
|/ | | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | Merge pull request #855 from galibert/master | gatecat | 2021-10-28 | 2 | -4/+3 |
|\ | | | | | mistral: Sync with yet another reorganization | ||||
| * | mistral: Sync with yet another reorganization | Olivier Galibert | 2021-10-28 | 2 | -4/+3 |
|/ | |||||
* | Merge pull request #852 from yrabbit/pr-gowin-alu | gatecat | 2021-10-22 | 3 | -6/+226 |
|\ | | | | | gowin: Add ALU support. | ||||
| * | gowin: Explicitly initialize the y in the cluster | YRabbit | 2021-10-22 | 1 | -0/+5 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: Add ALU support. | YRabbit | 2021-10-22 | 3 | -6/+221 |
|/ | | | | | | | | - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | interchange: Bump prjoxide version | gatecat | 2021-10-20 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #851 from galibert/master | gatecat | 2021-10-19 | 3 | -13/+14 |
|\ | | | | | mistral: Use the iterators | ||||
| * | Normalize formatting | Olivier Galibert | 2021-10-19 | 2 | -13/+17 |
| | | |||||
| * | mistral: Use the iterators | Olivier Galibert | 2021-10-19 | 2 | -12/+9 |
|/ | |||||
* | Merge pull request #848 from galibert/master | gatecat | 2021-10-17 | 2 | -1/+2 |
|\ | | | | | mistral: Support the new routes-to-bin intermediate tool generation | ||||
| * | Sync mistral version in CI | Olivier Galibert | 2021-10-17 | 1 | -1/+1 |
| | | |||||
| * | mistral: Support the new routes-to-bin intermediate tool generation | Olivier Galibert | 2021-10-17 | 1 | -0/+1 |
| | | |||||
* | | Merge pull request #849 from galibert/cyclonev-oscillator | gatecat | 2021-10-17 | 4 | -3/+15 |
|\ \ | |/ |/| | mistral: Add internal oscillator support | ||||
| * | mistral: Add internal oscillator support | Olivier Galibert | 2021-10-17 | 4 | -3/+15 |
|/ | |||||
* | Merge pull request #847 from galibert/master | gatecat | 2021-10-15 | 4 | -0/+17 |
|\ | | | | | mistral: Add support for cyclonev_hps_interface_mpu_general_purpose | ||||
| * | cyclonev_hps_interface_mpu_general_purpose: Use a id_ identifier | Olivier Galibert | 2021-10-15 | 2 | -1/+3 |
| | | |||||
| * | mistral: Add support for cyclonev_hps_interface_mpu_general_purpose | Olivier Galibert | 2021-10-14 | 3 | -0/+15 |
|/ | |||||
* | Merge pull request #845 from YosysHQ/gatecat/mlab-cluster-fix | gatecat | 2021-10-11 | 2 | -2/+9 |
|\ | | | | | mistral: Fix MLAB clustering | ||||
| * | mistral: Fix MLAB clustering | gatecat | 2021-10-11 | 2 | -2/+9 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | clangformat | gatecat | 2021-10-11 | 2 | -29/+42 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timing | gatecat | 2021-10-11 | 3 | -21/+256 |
|\ | | | | | mistral: very basic timing info | ||||
| * | mistral: very basic timing info | Lofty | 2021-10-10 | 4 | -22/+257 |
| | | |||||
* | | Merge pull request #844 from pepijndevos/patch-2 | gatecat | 2021-10-10 | 1 | -2/+2 |
|\ \ | | | | | | | Gowin: more clearly mark dummy pips | ||||
| * | | Gowin: more clearly mark dummy pips | Pepijn de Vos | 2021-10-10 | 1 | -2/+2 |
|/ / | |||||
* | | Merge pull request #842 from yrabbit/delays | gatecat | 2021-10-09 | 3 | -12/+40 |
|\ \ | | | | | | | gowin: Replace the zero delays with reasonable values. | ||||
| * \ | Merge branch 'master' into delays | YRabbit | 2021-10-09 | 1 | -18/+6 |
| |\ \ | |||||
| * | | | gowin: Replace the zero delays with reasonable values. | YRabbit | 2021-10-09 | 3 | -12/+40 |
| | |/ | |/| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | | | router2: Disable criticality sorting towards end of routing | gatecat | 2021-10-09 | 1 | -1/+1 |
| |/ |/| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #841 from Ravenslofty/lofty/mistral-cleanup | gatecat | 2021-10-08 | 1 | -18/+6 |
|\ \ | |/ |/| | mistral: clean up bel init slightly | ||||
| * | mistral: clean up bel init slightly | Lofty | 2021-10-08 | 1 | -18/+6 |
|/ | |||||
* | hashlib: Support for std::array keys | gatecat | 2021-10-07 | 1 | -0/+13 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #839 from yrabbit/wide-luts | gatecat | 2021-10-07 | 7 | -9/+434 |
|\ | | | | | gowin: add support for wide LUTs. | ||||
| * | gowin: add support for wide LUTs. | YRabbit | 2021-10-07 | 7 | -9/+434 |
|/ | | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |