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* | | Merge pull request #350 from pepijndevos/newsliceDavid Shah2019-11-087-28/+42
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| * | | more formattingPepijn de Vos2019-11-081-2/+2
| * | | return FF_USED, formatting, correct INITPepijn de Vos2019-11-084-5/+20
| * | | dedicated output for LUT in GENERIC_SLICEPepijn de Vos2019-11-086-32/+31
* | | | cmake: Add boost system libraryDavid Shah2019-11-061-1/+1
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* | | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
* | | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
* | | ecp5: Allow setting drive strength for 3V3 IOsDavid Shah2019-10-261-0/+10
* | | ecp5: Add constids for new timing cell typesDavid Shah2019-10-262-0/+10
* | | ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-264-2/+10
* | | Merge branch 'master' of ssh.github.com:YosysHQ/nextpnrDavid Shah2019-10-251-8/+0
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| * \ \ Merge pull request #346 from xobs/fix-ice40-pregenerated-bbaDavid Shah2019-10-251-8/+0
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| | * | | ice40: cmake: fix build with pregenerated bba pathSean Cross2019-10-241-8/+0
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* / / / ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-253-1/+37
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* / / ecp5: Make database build depend on constids.incDavid Shah2019-10-201-2/+2
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| * add newline at eofMiodrag Milanovic2019-12-281-1/+1
| * Add options to enable/disable displayed elementsMiodrag Milanovic2019-12-209-16/+105
| * optimize and set orderMiodrag Milanovic2019-12-201-276/+236
| * clang formatMiodrag Milanovic2019-12-202-47/+132
| * Add all missing wiresMiodrag Milanovic2019-12-201-1/+1556
| * Add global wiresMiodrag Milanovic2019-12-154-19/+138
| * more pips on connection boxMiodrag Milanovic2019-12-151-0/+9
| * cleanup and formatingMiodrag Milanovic2019-12-152-13/+13
| * make it more simetricMiodrag Milanovic2019-12-151-13/+14
| * optimize and add some missing pipsMiodrag Milanovic2019-12-151-28/+17
| * cleanupMiodrag Milanovic2019-12-151-12/+7
| * cleanup wireMiodrag Milanovic2019-12-151-110/+3
| * move bel creation to gfx.ccMiodrag Milanovic2019-12-153-122/+101
| * fix formatingMiodrag Milanovic2019-12-143-110/+138
| * lot more pipsMiodrag Milanovic2019-12-141-4/+51
| * fixes and more pipsMiodrag Milanovic2019-12-142-1/+92
| * pips for alu, mult and memoryMiodrag Milanovic2019-12-141-3/+43
| * pips for iosMiodrag Milanovic2019-12-142-7/+134
| * propagate w and hMiodrag Milanovic2019-12-141-60/+96
| * pips for other type of connection boxMiodrag Milanovic2019-12-141-5/+17
| * more new wires addedMiodrag Milanovic2019-12-145-2/+214
| * ebr, mult and alu nice displayMiodrag Milanovic2019-12-142-8/+15
| * add moreMiodrag Milanovic2019-12-133-4/+44
| * new wires in dbMiodrag Milanovic2019-12-133-20/+498
| * added siologicMiodrag Milanovic2019-12-134-2/+63
| * Add many new wiresMiodrag Milanovic2019-12-134-0/+1250
| * clangformat runMiodrag Milanovic2019-12-084-330/+365
| * display IOs properlyMiodrag Milanovic2019-12-071-21/+5
| * More bels show properlyMiodrag Milanovic2019-12-071-43/+82
| * add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
| * Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
| * add more pipsMiodrag Milanovic2019-12-011-0/+49
| * Handle H00 and V00Miodrag Milanovic2019-11-111-6/+49
| * More pips and fix for V01Miodrag Milanovic2019-11-111-42/+170
| * cleanupMiodrag Milanovic2019-11-111-174/+78
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 19:43:48 +0000