Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Fixed JSON parser: negative values and line numbers | ZipCPU | 2018-08-14 | 1 | -9/+23 | |
| |/ / | | | | | | | | | | | | | | | | 1. jsonparse.cc now access negative numbers, properly parsing the sign 2. On any failure to properly parse, a line number is now provided with the unexpected character error | |||||
* | | | ecp5: Speedup router with slightly better estimates | David Shah | 2018-08-18 | 1 | -2/+2 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
* | | | do not break if there are no nets loaded from sym section | Miodrag Milanovic | 2018-08-18 | 1 | -4/+6 | |
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* | | | Added ability for static builds | Miodrag Milanovic | 2018-08-16 | 2 | -1/+15 | |
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* | | Merge pull request #48 from YosysHQ/placer_speedup | Eddie Hung | 2018-08-11 | 4 | -32/+66 | |
|\ \ | |/ |/| | placer: low hanging speedups | |||||
| * | Merge remote-tracking branch 'origin/master' into placer_speedup | Eddie Hung | 2018-08-10 | 12 | -36/+116 | |
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* | | Fix compile warning | Miodrag Milanovic | 2018-08-09 | 1 | -0/+2 | |
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* | | Expose log_always that will be displayed disregarding quite flag | Miodrag Milanovic | 2018-08-09 | 2 | -12/+10 | |
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* | | Added quiet mode for logging | Miodrag Milanovic | 2018-08-09 | 3 | -15/+28 | |
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* | | Fix MSVC compile | Miodrag Milanovic | 2018-08-09 | 1 | -0/+1 | |
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* | | Merge pull request #42 from YosysHQ/floorplan | David Shah | 2018-08-09 | 8 | -20/+86 | |
|\ \ | | | | | | | Add basic data structures for floorplanning | |||||
| * | | ecp5: Implement getPipLocation and related API | David Shah | 2018-08-09 | 1 | -1/+11 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | Add pip locations | Clifford Wolf | 2018-08-09 | 7 | -19/+61 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add Region struct | Clifford Wolf | 2018-08-09 | 1 | -0/+14 | |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵ | Eddie Hung | 2018-08-10 | 3 | -17/+18 | |
| | | | | | | | | | | | | std::array | |||||
| | * | std::vector::resize() not reserve() | Eddie Hung | 2018-08-09 | 1 | -1/+1 | |
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| | * | Make containers static | Eddie Hung | 2018-08-09 | 1 | -5/+7 | |
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| | * | Get rid of map lookup by borrowing udata to use as index into vector | Eddie Hung | 2018-08-09 | 1 | -19/+20 | |
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| | * | Try with vector | Eddie Hung | 2018-08-09 | 1 | -17/+47 | |
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* | | ice40: Speedup Arch::predictDelay() with pass-by-ref | Eddie Hung | 2018-08-08 | 1 | -1/+1 | |
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* | | Make loading works nice and use settings | Miodrag Milanovic | 2018-08-08 | 7 | -30/+36 | |
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* | | Merge pull request #46 from YosysHQ/use_settings | Miodrag Milanović | 2018-08-08 | 11 | -27/+68 | |
|\ \ | |/ |/| | Use settings for json and pcf | |||||
| * | Use settings for json and pcf | Miodrag Milanovic | 2018-08-08 | 11 | -27/+68 | |
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* | Merge pull request #45 from YosysHQ/constids | Clifford Wolf | 2018-08-08 | 31 | -553/+285 | |
|\ | | | | | Get rid of PortPin and BelType | |||||
| * | Merge branch 'master' of github.com:YosysHQ/nextpnr into constids | Clifford Wolf | 2018-08-08 | 29 | -913/+1270 | |
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* | | Merge pull request #44 from YosysHQ/improve_timing_spec | David Shah | 2018-08-08 | 10 | -140/+374 | |
|\ \ | | | | | | | Speed up budget allocator using topographical ordering and update cell timing API | |||||
| * | | ice40: Add error for unknown cell type when getting timing info | David Shah | 2018-08-08 | 1 | -1/+3 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | docs: Update Arch API Cell Timing docs | David Shah | 2018-08-08 | 1 | -6/+4 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | timing: Remove unused variable | David Shah | 2018-08-08 | 1 | -1/+0 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | timing: Update to use getDelayNS | David Shah | 2018-08-08 | 1 | -11/+14 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | One more breadcrumb | Eddie Hung | 2018-08-08 | 1 | -0/+1 | |
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| * | | Leave comment behind about removing false paths | Eddie Hung | 2018-08-08 | 1 | -1/+1 | |
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| * | | clangformat | David Shah | 2018-08-08 | 1 | -6/+12 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | Arch API: Removing Arch::isIOCell | David Shah | 2018-08-08 | 5 | -10/+0 | |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | Unfurl comments for clangformat | Eddie Hung | 2018-08-08 | 1 | -28/+12 | |
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| * | | Disable assign_budget() after placement legalisation, unless slack redist | Eddie Hung | 2018-08-08 | 1 | -1/+4 | |
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| * | | Merge branch 'master' into improve_timing_spec | Eddie Hung | 2018-08-08 | 1 | -0/+12 | |
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| * | | | Also include TMG_GEN_CLOCK as a timing startpoint | Eddie Hung | 2018-08-08 | 1 | -3/+2 | |
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| * | | | ice40: Add timing arcs through global buffers | David Shah | 2018-08-08 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | timing: Debugging implementation of new timing API | David Shah | 2018-08-08 | 2 | -5/+10 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | ice40: Timing arch fix | David Shah | 2018-08-08 | 1 | -3/+17 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | timing: Update to new use API (currently broken) | David Shah | 2018-08-08 | 5 | -19/+33 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | Arch API: New specification for timing port classes | David Shah | 2018-08-08 | 7 | -35/+66 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | common: Add TimingPortClass | David Shah | 2018-08-08 | 1 | -1/+14 | |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | Cleanup nesting | Eddie Hung | 2018-08-06 | 1 | -59/+59 | |
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| * | | | Do less work if update flag is false | Eddie Hung | 2018-08-06 | 1 | -6/+6 | |
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| * | | | clangformat | Eddie Hung | 2018-08-06 | 4 | -51/+57 | |
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| * | | | Also add PLL outputs as timing startpoints | Eddie Hung | 2018-08-06 | 1 | -15/+3 | |
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| * | | | Add Arch::isIOCell() to ecp5 and generic | Eddie Hung | 2018-08-06 | 3 | -0/+10 | |
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| * | | | Remove old timing code | Eddie Hung | 2018-08-06 | 1 | -88/+0 | |
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