| Commit message (Collapse) | Author | Age | Files | Lines |
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gowin: add PLL pins processing
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Until a comprehensive clock router is developed, the order in which
private cases are handled is important.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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viaduct: Fix constant connectivity
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Signed-off-by: gatecat <gatecat@ds0.me>
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api: Make NetInfo* of checkPipAvailForNet const
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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gowin: add information about pin configurations
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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ecp5: Fix Python bindings for pip iterators
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Signed-off-by: gatecat <gatecat@ds0.me>
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Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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gowin: mark the PLL ports that are not in use
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Unused ports are deactivated by special fuse combinations, rather than
being left dangling in the air.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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gowin: add support for a more common chip
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The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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gowin: add initial PLL support
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Replacing snprintf() with ctx->idf() in PLL commit, but not yet a
complete overhaul.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.
Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Fix "implicit copy constructor for 'Property' is deprecated"
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Fix python version in CI
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Signed-off-by: gatecat <gatecat@ds0.me>
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Support windows line endings in constraints for nextpnr-gowin
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Correct Not Equal operator implementation in ice40
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I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
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nexus: Transform registered output parameters
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Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B
Pseudo dual ported:
OUTREG -> OUT_REGMODE_B
Single ported:
OUTREG -> OUT_REGMODE_A
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fabulous: Add support for the CLB muxes
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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ice40: Fix handling of carry out route-thru via 25,14
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Signed-off-by: gatecat <gatecat@ds0.me>
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Fix runtime segmentation fault
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disable null pointer dereference!
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Support cross-domain clock relations in timing analyser
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paths, formatted code
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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