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* Change makefiles to build a FPGA interchange BBA.Keith Rothman2021-02-174-16/+106
* Add examples invoking FPGA interchange nextpnr.Keith Rothman2021-02-1711-0/+152
* Continue fixes.Keith Rothman2021-02-176-23/+97
* Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
* Add initial site router.Keith Rothman2021-02-174-6/+813
* Working on standing up initial constraints system.Keith Rothman2021-02-178-25/+886
* Merge pull request #589 from litghost/add_bits_librarygatecat2021-02-172-0/+124
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| * Add a Bits utility library.Keith Rothman2021-02-172-0/+124
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* Update docs/archapi.mdgatecat2021-02-171-2/+2
* Merge pull request #587 from YosysHQ/gatecat/generic-vccgatecat2021-02-172-5/+7
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| * generic: Don't generate Vcc if not neededgatecat2021-02-172-5/+7
* | clangformatgatecat2021-02-171-3/+4
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* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-172-13/+274
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| * Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-162-13/+266
* | Merge pull request #585 from YosysHQ/gatecat/remove-ivbfcgatecat2021-02-1724-287/+170
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| * Remove isValidBelForCellgatecat2021-02-1624-287/+170
* | Bump test submodulegatecat2021-02-161-0/+0
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* Merge pull request #583 from litghost/add_fpga_interchange_front_and_backendgatecat2021-02-1611-7/+909
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| * Pull in fix for out of source builds.Keith Rothman2021-02-151-0/+0
| * Move CMake logic into fpga-interchange-schema.Keith Rothman2021-02-152-13/+1
| * Small fixes from review.Keith Rothman2021-02-152-2/+2
| * Add libcapnp-dev for FPGA interchange compilation support.Keith Rothman2021-02-151-1/+2
| * Add FPGA interchange frontend and backend.Keith Rothman2021-02-157-5/+915
| * Add interchange schema 3rdparty.Keith Rothman2021-02-152-0/+3
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* Merge pull request #584 from YosysHQ/gatecat/generic-belpingatecat2021-02-157-5/+40
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| * generic: Update docsgatecat2021-02-151-2/+10
| * generic: Add bel pin mapping testgatecat2021-02-152-0/+1
| * generic: Add APIs for controlling cell->bel pin mappinggatecat2021-02-154-3/+29
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* Merge pull request #578 from YosysHQ/machxo2-rebasegatecat2021-02-1538-3/+4511
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| * ci: Bump prjtrellis versiongatecat2021-02-121-1/+1
| * Fix bad rebasegatecat2021-02-121-2/+1
| * machxo2: Misc tidying upgatecat2021-02-122-8/+4
| * machxo2: Python bindings and stub GUIgatecat2021-02-129-6/+346
| * machxo2: Use snake_case for non-ArchAPI functionsgatecat2021-02-124-63/+63
| * machxo2: Use IdStringLists in earnestgatecat2021-02-122-76/+70
| * machxo2: Update with Arch API changesgatecat2021-02-129-468/+119
| * machxo2: Prepare README.md for first PR.William D. Jones2021-02-121-4/+36
| * machxo2: Add prefix parameter to simtest.sh. Remove show command fromWilliam D. Jones2021-02-123-40/+43
| * machxo2: Add prefix parameter to simple.sh. Update README.md.William D. Jones2021-02-122-14/+14
| * machxo2: Fill in more about mitertest.sh in README.md and clean up a bit.William D. Jones2021-02-121-4/+27
| * machxo2: Add two new examples: blinky_ext and aforementioned UART.William D. Jones2021-02-123-0/+238
| * machxo2: auto-top does not work for smt miter either.William D. Jones2021-02-121-1/+1
| * machxo2: Fix unhelpful comment in mitertest.sh.William D. Jones2021-02-121-1/+0
| * machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Rem...William D. Jones2021-02-121-3/+7
| * machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules ...William D. Jones2021-02-123-37/+37
| * machxo2: Add prefix paramter to demo.sh.William D. Jones2021-02-124-22/+37
| * Add demo with RGB LEDmtnrbq2021-02-122-0/+43
| * machxo2: Fix packing when FF is driven by a constant; UART test core working ...William D. Jones2021-02-122-1/+3
| * machxo2: Add packing logic to handle FFs fed with constant value; UART test c...William D. Jones2021-02-123-5/+39