Commit message (Collapse) | Author | Age | Files | Lines | |
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* | refactor: ArcBounds -> BoundingBox | gatecat | 2022-12-07 | 26 | -57/+57 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1056 from YosysHQ/gatecat/generic-fix-consts | myrtle | 2022-12-06 | 1 | -0/+3 |
|\ | | | | | viaduct: Fix constant connectivity | ||||
| * | viaduct: Fix constant connectivity | gatecat | 2022-12-06 | 1 | -0/+3 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1054 from YosysHQ/gatecat/api-add-const | myrtle | 2022-12-04 | 13 | -17/+17 |
|\ | | | | | api: Make NetInfo* of checkPipAvailForNet const | ||||
| * | Unbreak CI | gatecat | 2022-12-02 | 1 | -5/+5 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | api: Make NetInfo* of checkPipAvailForNet const | gatecat | 2022-12-02 | 12 | -12/+12 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1048 from yrabbit/chipdb-cfg | myrtle | 2022-12-02 | 3 | -5/+23 |
|\ | | | | | gowin: add information about pin configurations | ||||
| * | gowin: update the apicula version | YRabbit | 2022-12-02 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | Merge branch 'master' into chipdb-cfg | YRabbit | 2022-12-02 | 1 | -2/+2 |
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* | | Merge pull request #1053 from YosysHQ/gatecat/pbfix | myrtle | 2022-11-28 | 1 | -2/+2 |
|\ \ | | | | | | | ecp5: Fix Python bindings for pip iterators | ||||
| * | | ecp5: Fix Python bindings for pip iterators | gatecat | 2022-11-28 | 1 | -2/+2 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | gowin: add information about pin configurations | YRabbit | 2022-11-25 | 2 | -4/+22 |
|/ | | | | | | | Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others. This allows a decision to be made about special network routing of such pins Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | Merge pull request #1045 from yrabbit/unused-ports | myrtle | 2022-11-20 | 2 | -0/+16 |
|\ | | | | | gowin: mark the PLL ports that are not in use | ||||
| * | gowin: mark the PLL ports that are not in use | YRabbit | 2022-11-20 | 2 | -0/+16 |
|/ | | | | | | | Unused ports are deactivated by special fuse combinations, rather than being left dangling in the air. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | Merge pull request #1042 from yrabbit/add-z1 | myrtle | 2022-11-12 | 1 | -1/+1 |
|\ | | | | | gowin: add support for a more common chip | ||||
| * | gowin: add support for a more common chip | YRabbit | 2022-11-12 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former chip is already very hard to buy, so let's experiment with a more affordable chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | | Merge pull request #1040 from yrabbit/pll-stage0 | myrtle | 2022-11-11 | 6 | -8/+210 |
|\| | | | | | gowin: add initial PLL support | ||||
| * | gowin: use ctx->idf() a bit | YRabbit | 2022-11-11 | 2 | -41/+17 |
| | | | | | | | | | | | | | | Replacing snprintf() with ctx->idf() in PLL commit, but not yet a complete overhaul. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | gowin: add initial PLL support | YRabbit | 2022-11-10 | 6 | -1/+227 |
| | | | | | | | | | | | | | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | | Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warning | myrtle | 2022-11-10 | 1 | -0/+1 |
|\ \ | | | | | | | Fix "implicit copy constructor for 'Property' is deprecated" | ||||
| * | | Fix "implicit copy constructor for 'Property' is deprecated" | gatecat | 2022-11-10 | 1 | -0/+1 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* / | fabulous: Tweak delay estimate | gatecat | 2022-11-10 | 1 | -0/+1 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1037 from YosysHQ/fix_python_ver | Miodrag Milanović | 2022-10-24 | 1 | -1/+2 |
|\ | | | | | Fix python version in CI | ||||
| * | Fix python version in CI | Miodrag Milanovic | 2022-10-24 | 1 | -1/+2 |
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* | Update CI script | Miodrag Milanovic | 2022-10-24 | 1 | -6/+6 |
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* | run clangformat | gatecat | 2022-10-17 | 2 | -7/+12 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1034 from lushaylabs/support-windows-crlf | myrtle | 2022-10-17 | 1 | -4/+4 |
|\ | | | | | Support windows line endings in constraints for nextpnr-gowin | ||||
| * | support windows line endings | Lushay Labs | 2022-10-09 | 1 | -4/+4 |
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* | | Merge pull request #1035 from tyler274/patch-1 | myrtle | 2022-10-17 | 1 | -1/+1 |
|\ \ | |/ |/| | Correct Not Equal operator implementation in ice40 | ||||
| * | Correct Not Equal operator implementation in ice40 | Tyler | 2022-10-17 | 1 | -1/+1 |
|/ | | | I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me. | ||||
* | Merge pull request #1032 from davidlattimore/registered-output-xform | myrtle | 2022-10-05 | 2 | -0/+9 |
|\ | | | | | nexus: Transform registered output parameters | ||||
| * | nexus: Transform registered output parameters | David Lattimore | 2022-10-05 | 2 | -0/+9 |
|/ | | | | | | | | | | | | Dual ported: OUTREG_A -> OUT_REGMODE_A OUTREG_B -> OUT_REGMODE_B Pseudo dual ported: OUTREG -> OUT_REGMODE_B Single ported: OUTREG -> OUT_REGMODE_A | ||||
* | Merge pull request #1031 from YosysHQ/gatecat/fab-next | myrtle | 2022-09-30 | 5 | -2/+130 |
|\ | | | | | fabulous: Add support for the CLB muxes | ||||
| * | fabulous: Pack, validity check and FASM support for muxes | gatecat | 2022-09-30 | 4 | -5/+84 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | fabulous: Add split MUX bels | gatecat | 2022-09-30 | 2 | -1/+50 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fix | myrtle | 2022-09-26 | 1 | -15/+21 |
|\ | | | | | ice40: Fix handling of carry out route-thru via 25,14 | ||||
| * | ice40: Fix handling of carry out route-thru via 25,14 | gatecat | 2022-09-26 | 1 | -15/+21 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #1029 from airskywater/airskywater-patch-1 | myrtle | 2022-09-24 | 1 | -0/+6 |
|\ | | | | | Fix runtime segmentation fault | ||||
| * | Modify code to meet the code style preferences | airskywater | 2022-09-24 | 1 | -4/+4 |
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| * | Add more sanity check for pointers | airskywater | 2022-09-24 | 1 | -0/+1 |
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| * | fix runtime segmentation fault | airskywater | 2022-09-24 | 1 | -0/+5 |
|/ | | | disable null pointer dereference! | ||||
* | Merge pull request #1019 from antmicro/support-clock-relations | myrtle | 2022-09-20 | 4 | -11/+300 |
|\ | | | | | Support cross-domain clock relations in timing analyser | ||||
| * | Added the --ignore-rel-clk option to control timing checks for cross-domain ↵ | Maciej Kurc | 2022-09-20 | 3 | -115/+108 |
| | | | | | | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Code cleanup | Maciej Kurc | 2022-08-31 | 2 | -68/+39 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added timing check for cross-domain paths for related clocks | Maciej Kurc | 2022-08-31 | 1 | -4/+104 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Augmented TimingAnalyser class with detection of clock to clock relations | Maciej Kurc | 2022-08-30 | 2 | -7/+225 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Fixed port timing classes of DCC ports in the Nexus architecture | Maciej Kurc | 2022-08-30 | 1 | -4/+11 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | | Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src | myrtle | 2022-09-20 | 2 | -0/+17 |
|\ \ | | | | | | | router2: Reserve source wire, too; ice40 fixes | ||||
| * | | ice40: implement checkPipAvailForNet | gatecat | 2022-09-20 | 1 | -0/+10 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | router2: Reserve source wire, too | gatecat | 2022-09-20 | 1 | -0/+7 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> |