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* | | | | Merge pull request #285 from whitequark/fix-missing-newlineDavid Shah2019-06-041-1/+1
|\ \ \ \ \ | |_|_|/ / |/| | | | Fix missing \n in log statement
| * | | | Fix missing \n in log statement.whitequark2019-06-041-1/+1
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* | | | Merge pull request #281 from whitequark/prefer-ports-as-netlabelDavid Shah2019-05-292-4/+13
|\ \ \ \ | | | | | | | | | | When choosing between labels for one net, always prefer ports
| * | | | When choosing between labels for one net, always prefer ports.whitequark2019-05-292-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Ports are already used in PCF and LPF files, so it is natural that the developer would use them for constraints as well. 2. Unpredictable (the set of netlabels nextpnr looks at depends on the optimizations during synthesis) net naming makes it impossible for code generators like nMigen to reliably apply clock constraints.
* | | | | Added explanation, fixes issue #278Miodrag Milanovic2019-05-271-1/+1
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* | | | Merge pull request #279 from YosysHQ/gui-no-aaMiodrag Milanović2019-05-253-4/+6
|\ \ \ \ | | | | | | | | | | option to disable anti aliasing in gui
| * | | | option to disable anti aliasing in guiMiodrag Milanovic2019-05-253-4/+6
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* | | | Merge pull request #169 from ajeakins/masterMiodrag Milanović2019-05-233-20/+24
|\ \ \ \ | | | | | | | | | | Fix device view not showing anything on macOS.
| * | | | Bring back check that GL contexts get the format requested.Adrian Jeakins2019-05-011-0/+13
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| * | | | Reduce GL shader version for wider compatibility.Adrian Jeakins2018-12-201-2/+2
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| * | | | Remove format versioning now this is set at the top level application.Adrian Jeakins2018-12-201-14/+0
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| * | | | Fix device view not showing anything on macOS.Adrian Jeakins2018-12-052-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | * Fix line shader when running under the core profile and make version match those elsewhere. * Make surface format version match the openGL functions we are using.
* | | | | Merge pull request #277 from mbuesch/assert_catch_warningDavid Shah2019-05-221-1/+1
|\ \ \ \ \ | |_|/ / / |/| | | | gui: Fix warning: catching polymorphic type by value
| * | | | gui: Fix warning: catching polymorphic type by valueMichael Buesch2019-05-201-1/+1
|/ / / / | | | | | | | | | | | | | | | | gui/application.cc: In member function ‘virtual bool nextpnr_ice40::Application::notify(QObject*, QEvent*)’: gui/application.cc:56:32: warning: catching polymorphic type ‘class nextpnr_ice40::assertion_failure’ by value [-Wcatch-value=]
* | | | Merge pull request #245 from twam/fix_osxDavid Shah2019-05-181-28/+28
|\ \ \ \ | | | | | | | | | | Use cmake's find_library to search for pytrellis.
| * | | | Use cmake's find_library to search for pytrellis.Tobias Müller2019-05-111-28/+28
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* | | | | Merge pull request #274 from smunaut/ice40_hfosc_trimDavid Shah2019-05-131-0/+5
|\ \ \ \ \ | |/ / / / |/| | | | ice40: Add support for HFOSC trimming
| * | | | ice40: Add support for HFOSC trimmingSylvain Munaut2019-05-131-0/+5
|/ / / / | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | Merge pull request #273 from YosysHQ/ecp5_mclkDavid Shah2019-05-103-0/+34
|\ \ \ \ | | | | | | | | | | ecp5: Fix USRMCLK primitive
| * | | | ecp5: Fix USRMCLK primitiveDavid Shah2019-05-103-0/+34
|/ / / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #261 from YosysHQ/pygenericDavid Shah2019-04-1930-40/+1473
|\ \ \ \ | |_|/ / |/| | | Python API for generic architecture
| * | | ci: Bump Yosys version for tcl argument supportDavid Shah2019-04-171-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ci: Run generic example simple.shDavid Shah2019-04-172-3/+4
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | pybindings: make errors in Python scripts stop nextpnr executionDavid Shah2019-04-172-3/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Disable GUI as it isn't supported yetDavid Shah2019-04-171-8/+5
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic/examples: Add FASM writer Python scriptDavid Shah2019-04-179-38/+92
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | pybindings: Fix use of import in user scriptsDavid Shah2019-04-171-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Fix predictDelayDavid Shah2019-04-041-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Router param tweaksDavid Shah2019-04-041-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Cell timing supportDavid Shah2019-04-048-12/+152
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Improve exampleDavid Shah2019-04-042-17/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: GUI Python bindingsDavid Shah2019-04-037-10/+70
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Add a few more bindingsDavid Shah2019-04-021-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Adding API usage documentationDavid Shah2019-04-021-0/+99
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Simple working exampleDavid Shah2019-04-0211-26/+66
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Simple procedural example worksDavid Shah2019-04-024-7/+87
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Add a simple packer for generic SLICEs and IOBsDavid Shah2019-04-027-6/+597
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Add synth_generic.tclDavid Shah2019-04-023-3/+34
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Add simple primitive libraryDavid Shah2019-04-022-0/+71
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Place a single SLICEDavid Shah2019-04-024-34/+29
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | generic: Python bindings for arch constructionDavid Shah2019-04-021-0/+56
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | python: Named argument supportDavid Shah2019-04-023-0/+32
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | python: Infrastructure for generic arch Python APIDavid Shah2019-04-023-0/+170
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #270 from smunaut/sb_io_conflictDavid Shah2019-04-172-2/+38
|\ \ \ \ | | | | | | | | | | SB IO conflict checks
| * | | | ice40: Check for SB_IO shared wires conflicts in isValidBelForCellSylvain Munaut2019-04-171-0/+36
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | | ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrsSylvain Munaut2019-04-171-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | Merge pull request #269 from smunaut/pll_gb_placeDavid Shah2019-04-171-13/+86
|\ \ \ \ \ | |/ / / / |/| | | | PLL GB usage and placement fix
| * | | | ice40: Only create padin gbuf for PLLs if global output actually usedSylvain Munaut2019-04-171-11/+38
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | | ice40: Take placed SB_GBs into account when placing PLLsSylvain Munaut2019-04-161-9/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the PLLs drive global networks, we need to account for already existing and placed SB_GBs when trying to place/pack them. Theses can be user instanciated SB_GBs with BEL attribute, or SB_GB_IOs that got converted during the IO packing. This patch assumes that: - If a PLL is used the output A global network is always used, even if there is no connection to the global output pin - If a PLL with a singe output is used, then the B output global network is still free to be used by whatever. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | Merge pull request #267 from noopwafel/lock-for-timingDavid Shah2019-04-161-0/+2
|\ \ \ \ \ | |/ / / / |/| | | | timing_opt: Add locks to optimise()
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