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| * | | leftover Q from before slice api changePepijn de Vos2019-11-181-4/+4
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* | | Fix typoDavid Shah2019-11-111-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | python: Add interactive.py for a REPL during PnRDavid Shah2019-11-111-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #350 from pepijndevos/newsliceDavid Shah2019-11-087-28/+42
|\ \ \ | | | | | | | | Dedicated output for LUT in GENERIC_SLICE
| * | | more formattingPepijn de Vos2019-11-081-2/+2
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| * | | return FF_USED, formatting, correct INITPepijn de Vos2019-11-084-5/+20
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| * | | dedicated output for LUT in GENERIC_SLICEPepijn de Vos2019-11-086-32/+31
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* | | | cmake: Add boost system libraryDavid Shah2019-11-061-1/+1
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Allow setting drive strength for 3V3 IOsDavid Shah2019-10-261-0/+10
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Add constids for new timing cell typesDavid Shah2019-10-262-0/+10
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-264-2/+10
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge branch 'master' of ssh.github.com:YosysHQ/nextpnrDavid Shah2019-10-251-8/+0
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| * \ \ Merge pull request #346 from xobs/fix-ice40-pregenerated-bbaDavid Shah2019-10-251-8/+0
| |\ \ \ | | | | | | | | | | ice40: cmake: fix build with pregenerated bba path
| | * | | ice40: cmake: fix build with pregenerated bba pathSean Cross2019-10-241-8/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building using non-pregenerated bba files, the rule to create bbasm files gets called twice: once unconditionally, and once as part of the conditional that determines we're not using a pregenerated bba path. If we _are_ using a pregenerated bba path, then this rule gets called anyway, resulting in a build error. Remove the duplicate, unconditional creation of the bba file generation, to fix the build when using pregenerated files, and to speed up the build when not using pregenerated files. Signed-off-by: Sean Cross <sean@xobs.io>
* / / / ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-253-1/+37
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / / ecp5: Make database build depend on constids.incDavid Shah2019-10-201-2/+2
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * add newline at eofMiodrag Milanovic2019-12-281-1/+1
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| * Add options to enable/disable displayed elementsMiodrag Milanovic2019-12-209-16/+105
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| * optimize and set orderMiodrag Milanovic2019-12-201-276/+236
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| * clang formatMiodrag Milanovic2019-12-202-47/+132
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| * Add all missing wiresMiodrag Milanovic2019-12-201-1/+1556
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| * Add global wiresMiodrag Milanovic2019-12-154-19/+138
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| * more pips on connection boxMiodrag Milanovic2019-12-151-0/+9
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| * cleanup and formatingMiodrag Milanovic2019-12-152-13/+13
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| * make it more simetricMiodrag Milanovic2019-12-151-13/+14
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| * optimize and add some missing pipsMiodrag Milanovic2019-12-151-28/+17
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| * cleanupMiodrag Milanovic2019-12-151-12/+7
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| * cleanup wireMiodrag Milanovic2019-12-151-110/+3
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| * move bel creation to gfx.ccMiodrag Milanovic2019-12-153-122/+101
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| * fix formatingMiodrag Milanovic2019-12-143-110/+138
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| * lot more pipsMiodrag Milanovic2019-12-141-4/+51
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| * fixes and more pipsMiodrag Milanovic2019-12-142-1/+92
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| * pips for alu, mult and memoryMiodrag Milanovic2019-12-141-3/+43
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| * pips for iosMiodrag Milanovic2019-12-142-7/+134
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| * propagate w and hMiodrag Milanovic2019-12-141-60/+96
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| * pips for other type of connection boxMiodrag Milanovic2019-12-141-5/+17
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| * more new wires addedMiodrag Milanovic2019-12-145-2/+214
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| * ebr, mult and alu nice displayMiodrag Milanovic2019-12-142-8/+15
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| * add moreMiodrag Milanovic2019-12-133-4/+44
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| * new wires in dbMiodrag Milanovic2019-12-133-20/+498
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| * added siologicMiodrag Milanovic2019-12-134-2/+63
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| * Add many new wiresMiodrag Milanovic2019-12-134-0/+1250
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| * clangformat runMiodrag Milanovic2019-12-084-330/+365
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| * display IOs properlyMiodrag Milanovic2019-12-071-21/+5
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| * More bels show properlyMiodrag Milanovic2019-12-071-43/+82
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| * add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
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| * Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
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| * add more pipsMiodrag Milanovic2019-12-011-0/+49
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