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* Start making use of getBelPinsForCellPin APIgatecat2021-02-101-24/+68
| | | | | | | | | | | | This replaces getNetinfoSinkWire with 3 new functions for different use cases. At the moment all existing code has been moved to getNetinfoSinkWire with phys_idx=0 so the build doesn't break; but this won't yet function properly with more than one sink. But it provides a base on which to work on refactoring the routers to support this case. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove the unused CellInfo::pins fieldgatecat2021-02-101-20/+0
| | | | | | | | | | | No arches ever actually used this to implement a Cell->Bel pin mapping, and in practice if any did try they would inevitably hit bitrot. This field had limited use in practice as it is necessary to also support cases where one cell pin maps to more than one bel pin. Removing this old field is the first step towards developing a new API for this. Signed-off-by: gatecat <gatecat@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-2/+2
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-5/+29
| | | | | | | This is a complete implementation of IdStringList for ECP5; excluding the GUI (which you will have to disable for it to build). Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-3/+19
| | | | | | | | | | | This uses the new IdStringList API to store bel names for the ECP5. Note that other arches and the GUI do not yet build with this proof-of-concept patch. getBelByName still uses the old implementation and could be more efficiently implemented with further development. Signed-off-by: D. Shah <dave@ds0.me>
* common: First pass at IdStringList methodsD. Shah2021-02-021-0/+35
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Add global networksDavid Shah2020-11-301-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nextpnr: Improve error reporting in Context::checkDavid Shah2020-11-261-17/+67
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add a warning when floorplan constraint doesn't matchDavid Shah2020-08-121-1/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2020-06-121-12/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-0/+19
| | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* Allow constraining non-leaf cells to regionsDavid Shah2019-12-271-1/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Preserve hierarchy through packingDavid Shah2019-12-271-0/+73
| | | | Signed-off-by: David Shah <dave@ds0.me>
* python: Adding helper functions for netlist modificationDavid Shah2019-09-151-0/+85
| | | | Signed-off-by: David Shah <dave@ds0.me>
* json: Add support for net aliasesDavid Shah2019-09-131-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: New Property interfaceDavid Shah2019-08-051-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Major Property improvements for common and iCE40David Shah2019-08-051-22/+78
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformat runMiodrag Milanovic2019-06-251-24/+23
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* Save/restore net strengthMiodrag Milanovic2019-06-071-5/+7
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* Restore routing from jsonMiodrag Milanovic2019-06-071-1/+21
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* CleanupMiodrag Milanovic2019-06-071-2/+3
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* Cleanup and fixes, flow works nowMiodrag Milanovic2019-06-071-4/+31
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* WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+66
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* generic: GUI Python bindingsDavid Shah2019-04-031-0/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* common: Add early return path to getNetinfoRouteDelay for fully unrouted netsDavid Shah2019-03-221-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Python helper functions for floorplanningDavid Shah2019-03-221-0/+21
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing: Improve clock constraint log outputDavid Shah2018-11-261-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Improve message spacingEddie Hung2018-11-141-1/+1
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* Timing fixesDavid Shah2018-11-141-0/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+26
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| * Add more nameOf() convenience methodsClifford Wolf2018-11-131-0/+24
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * flush logs when throwing an assertion_failureClifford Wolf2018-11-101-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | timing: Add support for clock constraintsDavid Shah2018-11-121-0/+9
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Working on multi-clock analysisDavid Shah2018-11-121-7/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Implementing parts of new timing APIDavid Shah2018-11-121-0/+94
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Debugging DRAM packingDavid Shah2018-10-011-0/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Use ArchNetInfo to mark global nets to ignoreDavid Shah2018-09-291-6/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Global router produces a working bitstreamDavid Shah2018-09-291-0/+7
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-8/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformat for stuff I've touchedEddie Hung2018-07-311-2/+2
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* Modify the getNetinfo*() functions and getBudgetOverride() to not useEddie Hung2018-07-311-6/+5
| | | | user_idx and to take a PortRef& instead
* Modify predictDelay signatureEddie Hung2018-07-301-1/+1
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* Add predictDelay Arch APIClifford Wolf2018-07-301-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* common: Fix getNetinfoRouteDelay when net has no driverDavid Shah2018-07-301-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add fallback to estimateDelay() in getNetinfoRouteDelay()Clifford Wolf2018-07-231-1/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move common patterns from router1 to Context APIClifford Wolf2018-07-221-0/+56
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Revert "Refactor proxies to nextpnr."Sergiusz Bazanski2018-07-141-11/+0
| | | | This reverts commit 9b17fe385cf7e8d3025747b5f7c7822ac2d99920.
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