Commit message (Collapse) | Author | Age | Files | Lines | |
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* | C++17 compatibility: Don't use std::random_shuffle | Per Grön | 2020-12-30 | 1 | -4/+10 |
| | | | | std::random_shuffle deprecated in C++14 and was removed in C++17. | ||||
* | Only print filenames for now, default on | Ross Schlaikjer | 2020-08-30 | 1 | -4/+2 |
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* | Add option to print critical path source code | Ross Schlaikjer | 2020-08-30 | 1 | -0/+5 |
| | | | | | | | In order to make debugging the critical path easier, add an option that will log the location each net was defined, if known. If the file that contains the definition is known, and is readable, also print the part of the source HDL responsible for the signal definition. | ||||
* | Port nextpnr-{ice40,ecp5} to WASI. | whitequark | 2020-05-23 | 1 | -0/+14 |
| | | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches. | ||||
* | svg: Basic SVG graphics rendering | David Shah | 2020-02-15 | 1 | -0/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Router2 test integration | David Shah | 2020-02-03 | 1 | -0/+22 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Preserve hierarchy through packing | David Shah | 2019-12-27 | 1 | -0/+7 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | python: Add bindings for hierarchy structures | David Shah | 2019-12-27 | 1 | -4/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | First pass at data structures for hierarchy | David Shah | 2019-12-27 | 1 | -2/+29 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | frontend/base: Functions for port import | David Shah | 2019-12-27 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | sdf: Working on support for CVC | David Shah | 2019-10-24 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | sdf: Add basic support for writing SDF files | David Shah | 2019-10-19 | 1 | -0/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | python: Adding helper functions for netlist modification | David Shah | 2019-09-15 | 1 | -1/+23 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | json: Add support for net aliases | David Shah | 2019-09-13 | 1 | -0/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: New Property interface | David Shah | 2019-08-05 | 1 | -0/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Major Property improvements for common and iCE40 | David Shah | 2019-08-05 | 1 | -27/+88 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Switching from std to boost fix crash | Miodrag Milanovic | 2019-07-05 | 1 | -4/+4 |
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* | clangformat run | Miodrag Milanovic | 2019-06-25 | 1 | -17/+20 |
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* | Preserve ports | Miodrag Milanovic | 2019-06-21 | 1 | -0/+3 |
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* | moved some context variables to settings | Miodrag Milanovic | 2019-06-15 | 1 | -7/+11 |
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* | No need for settings class | Miodrag Milanovic | 2019-06-15 | 1 | -0/+13 |
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* | Use properties for settings and save in json | Miodrag Milanovic | 2019-06-12 | 1 | -1/+1 |
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* | Save top level attrs and store current step | Miodrag Milanovic | 2019-06-07 | 1 | -0/+3 |
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* | Cleanup | Miodrag Milanovic | 2019-06-07 | 1 | -2/+2 |
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* | WIP saving/loading attributes | Miodrag Milanovic | 2019-06-07 | 1 | -0/+3 |
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* | Added support for attributes/properties types | Miodrag Milanovic | 2019-06-01 | 1 | -2/+37 |
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* | generic: Cell timing support | David Shah | 2019-04-04 | 1 | -3/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | generic: GUI Python bindings | David Shah | 2019-04-03 | 1 | -0/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add Python helper functions for floorplanning | David Shah | 2019-03-22 | 1 | -0/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | clangformat | David Shah | 2018-11-16 | 1 | -4/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-14 | 1 | -1/+1 |
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| * | [common] Fix typo in Loc::operator!=() | Eddie Hung | 2018-11-13 | 1 | -1/+1 |
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* | | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 1 | -3/+14 |
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| * | Add more nameOf() convenience methods | Clifford Wolf | 2018-11-13 | 1 | -2/+12 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add checkers and assertions to router1 and other improvements | Clifford Wolf | 2018-11-10 | 1 | -1/+2 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | timing: Add support for clock constraints | David Shah | 2018-11-12 | 1 | -1/+4 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | timing: Multiple clock analysis | David Shah | 2018-11-12 | 1 | -0/+6 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Working on multi-clock analysis | David Shah | 2018-11-12 | 1 | -5/+7 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | timing: Implementing parts of new timing API | David Shah | 2018-11-12 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | timing: Working on a timing constraint API | David Shah | 2018-11-12 | 1 | -0/+103 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | gui: improved FPGAViewWidget::paintGL() performance | Mateusz Zalega | 2018-10-23 | 1 | -0/+14 |
| | | | | | | | | | Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking the most time during paintGL() calls. I've been able to take the CPU usage down to about 1/4 of its previous values by caching elements in VBOs and updating them only after subsequent calls to renderGraphicElement(). Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com> | ||||
* | Add pip locations | Clifford Wolf | 2018-08-09 | 1 | -0/+6 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add Region struct | Clifford Wolf | 2018-08-09 | 1 | -0/+14 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge branch 'master' of github.com:YosysHQ/nextpnr into constids | Clifford Wolf | 2018-08-08 | 1 | -1/+17 |
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| * | Merge pull request #44 from YosysHQ/improve_timing_spec | David Shah | 2018-08-08 | 1 | -1/+14 |
| |\ | | | | | | | Speed up budget allocator using topographical ordering and update cell timing API | ||||
| | * | Arch API: New specification for timing port classes | David Shah | 2018-08-08 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | common: Add TimingPortClass | David Shah | 2018-08-08 | 1 | -1/+14 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | | Add ctx->settings | Clifford Wolf | 2018-08-08 | 1 | -0/+3 |
| |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* / | Get rid of PortPin and BelType (ice40, generic, docs) | Clifford Wolf | 2018-08-08 | 1 | -3/+3 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) | Clifford Wolf | 2018-08-05 | 1 | -0/+7 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> |