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* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-0/+14
| | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* svg: Basic SVG graphics renderingDavid Shah2020-02-151-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router2 test integrationDavid Shah2020-02-031-0/+22
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Preserve hierarchy through packingDavid Shah2019-12-271-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* python: Add bindings for hierarchy structuresDavid Shah2019-12-271-4/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* First pass at data structures for hierarchyDavid Shah2019-12-271-2/+29
| | | | Signed-off-by: David Shah <dave@ds0.me>
* frontend/base: Functions for port importDavid Shah2019-12-271-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sdf: Working on support for CVCDavid Shah2019-10-241-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* sdf: Add basic support for writing SDF filesDavid Shah2019-10-191-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* python: Adding helper functions for netlist modificationDavid Shah2019-09-151-1/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* json: Add support for net aliasesDavid Shah2019-09-131-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: New Property interfaceDavid Shah2019-08-051-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Major Property improvements for common and iCE40David Shah2019-08-051-27/+88
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Switching from std to boost fix crashMiodrag Milanovic2019-07-051-4/+4
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* clangformat runMiodrag Milanovic2019-06-251-17/+20
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* Preserve portsMiodrag Milanovic2019-06-211-0/+3
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* moved some context variables to settingsMiodrag Milanovic2019-06-151-7/+11
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* No need for settings classMiodrag Milanovic2019-06-151-0/+13
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* Use properties for settings and save in jsonMiodrag Milanovic2019-06-121-1/+1
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* Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+3
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* CleanupMiodrag Milanovic2019-06-071-2/+2
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* WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+3
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* Added support for attributes/properties typesMiodrag Milanovic2019-06-011-2/+37
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* generic: Cell timing supportDavid Shah2019-04-041-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: GUI Python bindingsDavid Shah2019-04-031-0/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Python helper functions for floorplanningDavid Shah2019-03-221-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-11-161-4/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-141-1/+1
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| * [common] Fix typo in Loc::operator!=()Eddie Hung2018-11-131-1/+1
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* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-3/+14
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| * Add more nameOf() convenience methodsClifford Wolf2018-11-131-2/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add checkers and assertions to router1 and other improvementsClifford Wolf2018-11-101-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | timing: Add support for clock constraintsDavid Shah2018-11-121-1/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Multiple clock analysisDavid Shah2018-11-121-0/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Working on multi-clock analysisDavid Shah2018-11-121-5/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Implementing parts of new timing APIDavid Shah2018-11-121-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | timing: Working on a timing constraint APIDavid Shah2018-11-121-0/+103
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* gui: improved FPGAViewWidget::paintGL() performanceMateusz Zalega2018-10-231-0/+14
| | | | | | | | | Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking the most time during paintGL() calls. I've been able to take the CPU usage down to about 1/4 of its previous values by caching elements in VBOs and updating them only after subsequent calls to renderGraphicElement(). Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com>
* Add pip locationsClifford Wolf2018-08-091-0/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Region structClifford Wolf2018-08-091-0/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-1/+17
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-1/+14
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * common: Add TimingPortClassDavid Shah2018-08-081-1/+14
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | Add ctx->settingsClifford Wolf2018-08-081-0/+3
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-3/+3
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-0/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add router1 cfg.useEstimate, improve getActualRouteDelayClifford Wolf2018-08-041-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' into slack_redist_freqEddie Hung2018-08-031-1/+1
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