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* netlist: Add PseudoCell APIgatecat2022-07-085-14/+50
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split up common into kernel,place,routegatecat2022-04-0811-0/+5580
Signed-off-by: gatecat <gatecat@ds0.me>