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* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-022-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix "implicit copy constructor for 'Property' is deprecated"gatecat2022-11-101-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* run clangformatgatecat2022-10-171-6/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
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* Add more sanity check for pointersairskywater2022-09-241-0/+1
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* fix runtime segmentation faultairskywater2022-09-241-0/+5
| | | disable null pointer dereference!
* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-203-7/+289
|\ | | | | Support cross-domain clock relations in timing analyser
| * Added the --ignore-rel-clk option to control timing checks for cross-domain ↵Maciej Kurc2022-09-203-115/+108
| | | | | | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Code cleanupMaciej Kurc2022-08-311-64/+35
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | router2: Reserve source wire, toogatecat2022-09-201-0/+7
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* add missing overridesMiodrag Milanovic2022-08-221-3/+3
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* Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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* pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
| | | | | | | | bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement. Fixes #522 Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-103-4/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* netlist: Add PseudoCell APIgatecat2022-07-0813-44/+179
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* generic: Use arch_pybindings_sharedgatecat2022-07-041-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split up common into kernel,place,routegatecat2022-04-0874-0/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* parallel_refine: Fix compile error with some configsgatecat2022-03-191-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* BUGFIX: disable the thousands separatorYRabbit2022-03-161-1/+8
| | | | | | | The wire numbers are very large and it is undesirable to use a thousand separator there. This is a side effect of enabling locale. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Set the locale as early as possibleYRabbit2022-03-161-1/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2022-03-091-5/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing part of commit aee35768.Catherine2022-03-081-1/+4
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* Disable parallel refinement on WebAssembly.Catherine2022-03-052-1/+19
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* parallel_refine: New, parallelised placement refinement passgatecat2022-03-035-2/+1012
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* Switch to potentially-sparse net users arraygatecat2022-02-2714-260/+285
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* Add indexed_store container typegatecat2022-02-262-0/+267
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add IdStringList::concat overrides taking IdStringgatecat2022-02-201-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-186-172/+167
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-163-11/+10
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* run clangformatgatecat2022-02-031-3/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add GUI.YRabbit2022-01-292-0/+4
| | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Switched integer pair hashing function from DJB2 to CantorMaciej Kurc2022-01-111-2/+5
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* SSOArray: Implement move and assignment operatorsgatecat2021-12-301-0/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Refactor for faster performancegatecat2021-12-301-9/+8
| | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-198-11/+34
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Experimental timing-driven ripup supportgatecat2021-12-183-6/+103
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Improve timing heuristicgatecat2021-12-181-13/+25
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* python: Bind getBelLocation/getPipLocationgatecat2021-12-142-1/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Improve reservation debug logginggatecat2021-12-121-2/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #867 from mkj/mkj/routerspeed2gatecat2021-12-121-2/+1
|\ | | | | Improvements to ecp5 router speed
| * ecp5: Keep "visited" localMatt Johnston2021-12-121-2/+1
| | | | | | | | Otherwise it keeps growing boundless and slows down small arcs
* | router2: Error instead of hang in case of reservation conflictsgatecat2021-12-121-0/+3
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: Improved the random seed initialisation for the contextdx-mon2021-11-191-6/+4
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* router2: Disable criticality sorting towards end of routinggatecat2021-10-091-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 23:36:35 +0000