Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Don't assert on mixed domain paths in report | gatecat | 2022-05-22 | 1 | -5/+0 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | common: Correct a minor typo in the message | YRabbit | 2022-05-10 | 1 | -1/+1 |
| | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | prefine: Do full-tile swaps, too | gatecat | 2022-04-19 | 2 | -1/+100 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Move general parallel detail place code out of parallel_refine | gatecat | 2022-04-17 | 5 | -545/+730 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Split up common into kernel,place,route | gatecat | 2022-04-08 | 74 | -0/+0 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | parallel_refine: Fix compile error with some configs | gatecat | 2022-03-19 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | BUGFIX: disable the thousands separator | YRabbit | 2022-03-16 | 1 | -1/+8 |
| | | | | | | | The wire numbers are very large and it is undesirable to use a thousand separator there. This is a side effect of enabling locale. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | Set the locale as early as possible | YRabbit | 2022-03-16 | 1 | -1/+9 |
| | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | clangformat | gatecat | 2022-03-09 | 1 | -5/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Add missing part of commit aee35768. | Catherine | 2022-03-08 | 1 | -1/+4 |
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* | Disable parallel refinement on WebAssembly. | Catherine | 2022-03-05 | 2 | -1/+19 |
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* | parallel_refine: New, parallelised placement refinement pass | gatecat | 2022-03-03 | 5 | -2/+1012 |
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* | Switch to potentially-sparse net users array | gatecat | 2022-02-27 | 14 | -260/+285 |
| | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Add indexed_store container type | gatecat | 2022-02-26 | 2 | -0/+267 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Add IdStringList::concat overrides taking IdString | gatecat | 2022-02-20 | 1 | -0/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | refactor: New member functions to replace design_utils | gatecat | 2022-02-18 | 6 | -172/+167 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | refactor: New NetInfo and CellInfo constructors | gatecat | 2022-02-16 | 3 | -11/+10 |
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* | run clangformat | gatecat | 2022-02-03 | 1 | -3/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | gowin: Add GUI. | YRabbit | 2022-01-29 | 2 | -0/+4 |
| | | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
* | Switched integer pair hashing function from DJB2 to Cantor | Maciej Kurc | 2022-01-11 | 1 | -2/+5 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | SSOArray: Implement move and assignment operators | gatecat | 2021-12-30 | 1 | -0/+20 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | generic: Refactor for faster performance | gatecat | 2021-12-30 | 1 | -9/+8 |
| | | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | archapi: Use arbitrary rather than actual placement in predictDelay | gatecat | 2021-12-19 | 8 | -11/+34 |
| | | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | router1: Experimental timing-driven ripup support | gatecat | 2021-12-18 | 3 | -6/+103 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | router1: Improve timing heuristic | gatecat | 2021-12-18 | 1 | -13/+25 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | python: Bind getBelLocation/getPipLocation | gatecat | 2021-12-14 | 2 | -1/+8 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | router2: Improve reservation debug logging | gatecat | 2021-12-12 | 1 | -2/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #867 from mkj/mkj/routerspeed2 | gatecat | 2021-12-12 | 1 | -2/+1 |
|\ | | | | | Improvements to ecp5 router speed | ||||
| * | ecp5: Keep "visited" local | Matt Johnston | 2021-12-12 | 1 | -2/+1 |
| | | | | | | | | Otherwise it keeps growing boundless and slows down small arcs | ||||
* | | router2: Error instead of hang in case of reservation conflicts | gatecat | 2021-12-12 | 1 | -0/+3 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | common: Improved the random seed initialisation for the context | dx-mon | 2021-11-19 | 1 | -6/+4 |
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* | router2: Disable criticality sorting towards end of routing | gatecat | 2021-10-09 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | hashlib: Support for std::array keys | gatecat | 2021-10-07 | 1 | -0/+13 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Fix Cygwin build | gatecat | 2021-10-01 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Code formatting | Maciej Kurc | 2021-09-29 | 4 | -119/+87 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Brought back printout of critical path source file references, added ↵ | Maciej Kurc | 2021-09-29 | 3 | -28/+74 |
| | | | | | | clk-to-q, source and setup segment types Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Shifted moving of data containers after printing | Maciej Kurc | 2021-09-28 | 1 | -11/+11 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Added a commandline option controlled writeout of per-net timing details | Maciej Kurc | 2021-09-28 | 4 | -9/+22 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Added description of the JSON report structure. | Maciej Kurc | 2021-09-28 | 1 | -1/+73 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Moved timing result report storage to the context, added its writeout to the ↵ | Maciej Kurc | 2021-09-28 | 6 | -282/+279 |
| | | | | | | current utilization and fmax report Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Added reporting critical paths in JSON format | Maciej Kurc | 2021-09-28 | 1 | -25/+49 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Decoupled critical path report generation from its printing | Maciej Kurc | 2021-09-28 | 1 | -134/+264 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Switched to JSON format for timing analysis report | Maciej Kurc | 2021-09-28 | 1 | -33/+81 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | Added writing a CSV report with timing analysis of each net branch | Maciej Kurc | 2021-09-28 | 4 | -6/+89 |
| | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | idstring: Add 'in' function | gatecat | 2021-09-27 | 1 | -0/+10 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #812 from antmicro/MacroCells | gatecat | 2021-09-27 | 2 | -4/+4 |
|\ | | | | | Convert macros to clusters for better placement | ||||
| * | Fix small isses and code formatting | Maciej Dudek | 2021-09-27 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | Adding MacroCell placement | Maciej Dudek | 2021-09-23 | 1 | -4/+3 |
| | | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | Adding support for MacroCells | Maciej Dudek | 2021-09-23 | 1 | -2/+3 |
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* | | router2: Allow overriding resource costs | gatecat | 2021-09-24 | 2 | -2/+9 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> |