| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).
While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add constant network support to FPGA interchange arch
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add dynamic bitarray to common library.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Change CellInfo in getBelPinsForCellPin to be const.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Run "make clangformat" to fix formatting in new Bits library.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Replace DelayInfo with DelayPair and DelayQuad
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Signed-off-by: gatecat <gatecat@ds0.me>
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Complete FPGA interchange Arch to the point where it can route a wire
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This library captures use of __builtin_popcount and __builtin_ctz on
GCC/clang and hopefully handles the MSVC case.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.
In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).
Longer term, removing this API makes things a bit cleaner for a new
validity checking API.
Signed-off-by: gatecat <gatecat@ds0.me>
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Support for cell pin to bel pin mappings
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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This replaces getNetinfoSinkWire with 3 new functions for different use
cases.
At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.
Signed-off-by: gatecat <gatecat@ds0.me>
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This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.
But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.
Signed-off-by: gatecat <gatecat@ds0.me>
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Add control to whether GenericFrontend splits IO ports.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Fix assertion failure when opening the GUI on an arch without any
decals.
Signed-off-by: gatecat <gatecat@ds0.me>
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Add design_loaded state variable.
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This is to decouple the command line flag "--json" and enable other
frontend's.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.
This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.
Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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This splits out the pure-virtual definition of the architecture API into
ArchAPI; leaving BaseArch to only provide default implementations (which
can now be completely opted out of by deriving from ArchAPI instead of
BaseArch).
Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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