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Age
Files
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Minor improvements in router1
Clifford Wolf
2018-11-11
1
-4
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+9
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Some router1 cleanups
Clifford Wolf
2018-11-10
1
-12
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+39
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flush logs when throwing an assertion_failure
Clifford Wolf
2018-11-10
1
-0
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+2
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Add checkers and assertions to router1 and other improvements
Clifford Wolf
2018-11-10
2
-42
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+280
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Fixes and cleanups in router1
Clifford Wolf
2018-11-10
1
-10
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+10
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Fix log msg typo
Clifford Wolf
2018-11-09
1
-1
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+1
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Improve router console output
Clifford Wolf
2018-11-09
1
-10
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+13
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Fixes and improvements in new router
Clifford Wolf
2018-11-09
2
-16
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+57
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Essentially a rewrite router1
Clifford Wolf
2018-11-09
2
-782
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+341
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Merge branch 'master' of github.com:YosysHQ/nextpnr into router_improve
Clifford Wolf
2018-11-09
13
-45
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+255
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Dispose of far too long routes earlier (use 3x est. delay as limit)
Clifford Wolf
2018-09-04
1
-12
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+21
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Merge pull request #105 from YosysHQ/placer1_tmg_ignore
Clifford Wolf
2018-11-13
1
-6
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+6
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[placer1] Tidy up logic
Eddie Hung
2018-11-13
1
-3
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+3
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[placer1] Actually check for TMG_IGNORE!
Eddie Hung
2018-11-10
1
-1
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+1
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[placer1] Ignore timing of TMG_IGNORE nets
Eddie Hung
2018-11-10
1
-5
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+5
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timing: Fix compile warning
David Shah
2018-11-12
1
-1
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+1
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timing: Add support for clock constraints
David Shah
2018-11-12
3
-4
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+35
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ecp5: Update arch to new timing API
David Shah
2018-11-12
1
-2
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+1
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timing: Fix Fmax for clocks with mixed edge usage
David Shah
2018-11-12
1
-10
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+11
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archapi: Add getDelayFromNS to improve timing algorithm portability
David Shah
2018-11-12
1
-3
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+3
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timing: Fix handling of clock inputs
David Shah
2018-11-12
1
-10
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+17
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timing: Don't include false startpoints in async paths
David Shah
2018-11-12
1
-2
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+8
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timing: Improve Fmax output and print cross-clock paths
David Shah
2018-11-12
3
-54
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+132
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timing: Multiple clock analysis
David Shah
2018-11-12
2
-9
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+31
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Working on multi-clock analysis
David Shah
2018-11-12
3
-185
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+272
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Working on adding multiple domains to timing analysis
David Shah
2018-11-12
1
-33
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+87
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timing: Implementing parts of new timing API
David Shah
2018-11-12
2
-0
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+96
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timing: Working on a timing constraint API
David Shah
2018-11-12
2
-1
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+105
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[timing] Fix combinational -> combinatorial
Eddie Hung
2018-11-11
1
-2
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+2
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[timing] Better messaging for failed timing analysis, allow --force to
Eddie Hung
2018-11-11
1
-1
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+4
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[common] placer to produce error when >1 cell->bel constraint
Eddie Hung
2018-11-08
1
-0
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+6
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gui: improved FPGAViewWidget::paintGL() performance
Mateusz Zalega
2018-10-23
1
-0
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+14
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Merge pull request #92 from YosysHQ/python-cmdline
David Shah
2018-10-21
2
-15
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+41
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common: Allow running Python scripts for all points in flow
David Shah
2018-10-17
2
-15
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+41
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Merge pull request #89 from YosysHQ/ecp5_bram
David Shah
2018-10-17
1
-0
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+6
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placer: Fix conflicts during constraint legalisation
David Shah
2018-10-11
1
-0
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+6
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Merge pull request #88 from YosysHQ/issue72
Eddie Hung
2018-10-11
1
-17
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+6
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[timing] Restore and skip false startpoints
Eddie Hung
2018-09-15
1
-17
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+6
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clangformat
David Shah
2018-10-01
1
-3
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+1
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ecp5: Debugging DRAM packing
David Shah
2018-10-01
2
-0
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+23
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design_utils: Adding some design helper functions
David Shah
2018-10-01
2
-0
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+36
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ecp5: Helper functions for distributed RAM support
David Shah
2018-10-01
1
-0
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+2
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Refactor chain finder to its own file
David Shah
2018-09-30
2
-1
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+70
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ecp5: Adding carry helper functions
David Shah
2018-09-30
2
-0
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+22
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clangformat
David Shah
2018-09-30
4
-11
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+19
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Merge pull request #81 from YosysHQ/ecp5_globals
David Shah
2018-09-30
2
-0
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+13
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ecp5: Use ArchNetInfo to mark global nets to ignore
David Shah
2018-09-29
2
-7
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+7
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ecp5: Global router produces a working bitstream
David Shah
2018-09-29
2
-0
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+13
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Make warnings visible in quiet mode
Miodrag Milanovic
2018-09-19
1
-2
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+0
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Merge pull request #66 from YosysHQ/issue65
Serge Bazanski
2018-08-26
1
-4
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+5
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