| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add getBelPinType to Python interface.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Split nextpnr.h to allow for linear inclusion.
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"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Abseil has a hard dependency on threads (not just in the build system
but in many places in the base libraries), so there is no way to use
it on WASI at the moment.
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Add absl::flat_hash_map.
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This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Use new timing engine for criticality
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add counter test for FPGA interchange
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add placement sanity check in placer_heap.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Also check return of placer1_refine.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).
While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add constant network support to FPGA interchange arch
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add dynamic bitarray to common library.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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