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| * | timing: Use new engine for HeAPgatecat2021-03-043-14/+19
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add support for critical path printinggatecat2021-03-042-0/+69
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Slack and criticality computationgatecat2021-03-042-0/+47
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Produce plausible Fmax figuregatecat2021-03-042-1/+12
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add Fmax printing for debugginggatecat2021-03-042-0/+23
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add backwards path walkinggatecat2021-03-043-1/+71
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add forward path walkinggatecat2021-03-042-0/+105
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Compute domain pairsgatecat2021-03-042-13/+59
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add port-domain trackinggatecat2021-03-043-1/+115
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add topological sort from Yosysgatecat2021-03-043-0/+130
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Import cell delays to our own structuresgatecat2021-03-042-0/+123
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Data structures for STA rewritegatecat2021-03-041-0/+122
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | router2: Fix vast perf drop when leaving bounding boxgatecat2021-03-081-1/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #604 from litghost/add_counter_testgatecat2021-03-031-0/+2
|\ \ | | | | | | Add counter test for FPGA interchange
| * | Initial LUT rotation logic.Keith Rothman2021-02-261-0/+2
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #605 from litghost/add_placement_sanity_checkgatecat2021-03-025-11/+106
|\ \ | |/ |/| Add placement sanity check in placer_heap.
| * Correct spelling of RAII and add missing check in unlock_early.Keith Rothman2021-03-011-10/+19
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use scope in router1/2 and placer1.Keith Rothman2021-03-014-10/+18
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fix latent bug with context locking in placer HeAP.Keith Rothman2021-02-262-10/+68
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add placement sanity check in placer_heap.Keith Rothman2021-02-261-1/+21
| | | | | | | | | | | | Also check return of placer1_refine. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Prevent trival misplacements in placer1.Keith Rothman2021-02-261-0/+12
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove unused advanced timing constraint APIgatecat2021-02-262-187/+0
| | | | | | | | | | | | | This API was simply an attractive nuisance as no code was ever developed to actually process timing constraints (other than clock constraints which use a different API). While I do want to consider basic false path support, among other things, in the near future; I plan for this to use a new API that doesn't add complexity to the BaseCtx/Context monstrosity and that is easier to use on the timing analysis side. Signed-off-by: gatecat <gatecat@ds0.me>
* Allow router2 to use routed but not fixed arcs.Keith Rothman2021-02-251-4/+54
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-253-6/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #591 from litghost/add_constant_networkgatecat2021-02-252-10/+9
|\ | | | | Add constant network support to FPGA interchange arch
| * Remove some signedness warnings.Keith Rothman2021-02-232-10/+9
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #597 from litghost/add_dynamic_bitarraygatecat2021-02-241-0/+79
|\ \ | | | | | | Add dynamic bitarray to common library.
| * | Fix some bugs found in review.Keith Rothman2021-02-241-5/+2
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add dynamic bitarray to common library.Keith Rothman2021-02-231-0/+82
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #595 from litghost/const_cell_infogatecat2021-02-231-2/+2
|\ \ \ | | |/ | |/| Change CellInfo in getBelPinsForCellPin to be const.
| * | Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-2/+2
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #596 from litghost/make_clang_formatgatecat2021-02-232-11/+16
|\ \ | |/ |/| Run "make clangformat" to fix formatting in new Bits library.
| * Run "make clangformat" to fix new Bits library.Keith Rothman2021-02-232-11/+16
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Refactor some common code to CellInfo methodsgatecat2021-02-236-38/+43
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | HeAP: Document legalise_placement_strict bettergatecat2021-02-231-3/+45
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Demote the 'no clocks' warning to info and make clearergatecat2021-02-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #592 from YosysHQ/gatecat/rework-delaygatecat2021-02-207-35/+98
|\ | | | | Replace DelayInfo with DelayPair and DelayQuad
| * python: Bindings for DelayPair and DelayQuadgatecat2021-02-191-0/+25
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-196-35/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-191-1/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #576 from litghost/add_cell_bel_pin_mappinggatecat2021-02-196-0/+443
|\ | | | | Complete FPGA interchange Arch to the point where it can route a wire
| * Use Bits library for bit instrisics.Keith Rothman2021-02-171-2/+4
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-0/+23
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Working on standing up initial constraints system.Keith Rothman2021-02-175-0/+418
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Expose ice40 arch placer-heap internal parameters.Balint Cristian2021-02-182-4/+32
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* Add a Bits utility library.Keith Rothman2021-02-172-0/+124
| | | | | | | This library captures use of __builtin_popcount and __builtin_ctz on GCC/clang and hopefully handles the MSVC case. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove isValidBelForCellgatecat2021-02-164-24/+38
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-155-173/+253
|\ | | | | Support for cell pin to bel pin mappings
| * router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 07:13:17 +0000