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* | | | timing: Don't include false startpoints in async pathsDavid Shah2018-11-121-2/+8
* | | | timing: Improve Fmax output and print cross-clock pathsDavid Shah2018-11-123-54/+132
* | | | timing: Multiple clock analysisDavid Shah2018-11-122-9/+31
* | | | Working on multi-clock analysisDavid Shah2018-11-123-185/+272
* | | | Working on adding multiple domains to timing analysisDavid Shah2018-11-121-33/+87
* | | | timing: Implementing parts of new timing APIDavid Shah2018-11-122-0/+96
* | | | timing: Working on a timing constraint APIDavid Shah2018-11-122-1/+105
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* | | [timing] Fix combinational -> combinatorialEddie Hung2018-11-111-2/+2
* | | [timing] Better messaging for failed timing analysis, allow --force toEddie Hung2018-11-111-1/+4
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* | [common] placer to produce error when >1 cell->bel constraintEddie Hung2018-11-081-0/+6
* | gui: improved FPGAViewWidget::paintGL() performanceMateusz Zalega2018-10-231-0/+14
* | Merge pull request #92 from YosysHQ/python-cmdlineDavid Shah2018-10-212-15/+41
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| * | common: Allow running Python scripts for all points in flowDavid Shah2018-10-172-15/+41
* | | Merge pull request #89 from YosysHQ/ecp5_bramDavid Shah2018-10-171-0/+6
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| * | placer: Fix conflicts during constraint legalisationDavid Shah2018-10-111-0/+6
* | | Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-17/+6
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| * | [timing] Restore and skip false startpointsEddie Hung2018-09-151-17/+6
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* | clangformatDavid Shah2018-10-011-3/+1
* | ecp5: Debugging DRAM packingDavid Shah2018-10-012-0/+23
* | design_utils: Adding some design helper functionsDavid Shah2018-10-012-0/+36
* | ecp5: Helper functions for distributed RAM supportDavid Shah2018-10-011-0/+2
* | Refactor chain finder to its own fileDavid Shah2018-09-302-1/+70
* | ecp5: Adding carry helper functionsDavid Shah2018-09-302-0/+22
* | clangformatDavid Shah2018-09-304-11/+19
* | Merge pull request #81 from YosysHQ/ecp5_globalsDavid Shah2018-09-302-0/+13
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| * | ecp5: Use ArchNetInfo to mark global nets to ignoreDavid Shah2018-09-292-7/+7
| * | ecp5: Global router produces a working bitstreamDavid Shah2018-09-292-0/+13
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* / Make warnings visible in quiet modeMiodrag Milanovic2018-09-191-2/+0
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* Merge pull request #66 from YosysHQ/issue65Serge Bazanski2018-08-261-4/+5
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| * Fix for min_slack == max_slack => bin_size == 0Eddie Hung2018-08-221-4/+5
* | Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-188-14/+118
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| * | Use emplace result for get,set of settingsMiodrag Milanovic2018-08-121-8/+8
| * | Read settings and check validityMiodrag Milanovic2018-08-112-6/+28
| * | Save settings and give nicer names to someMiodrag Milanovic2018-08-101-1/+9
| * | Use settings for placer1 and router1Miodrag Milanovic2018-08-097-13/+87
* | | Add stringf() helper functionClifford Wolf2018-08-182-0/+15
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* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-107-20/+54
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| * Fix compile warningMiodrag Milanovic2018-08-091-0/+2
| * Expose log_always that will be displayed disregarding quite flagMiodrag Milanovic2018-08-092-12/+10
| * Added quiet mode for loggingMiodrag Milanovic2018-08-093-15/+28
| * Fix MSVC compileMiodrag Milanovic2018-08-091-0/+1
| * Merge pull request #42 from YosysHQ/floorplanDavid Shah2018-08-093-4/+24
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| | * Add pip locationsClifford Wolf2018-08-093-4/+10
| | * Add Region structClifford Wolf2018-08-091-0/+14
* | | std::vector::resize() not reserve()Eddie Hung2018-08-091-1/+1
* | | Get rid of map lookup by borrowing udata to use as index into vectorEddie Hung2018-08-091-19/+20
* | | Try with vectorEddie Hung2018-08-091-17/+47
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* | Make loading works nice and use settingsMiodrag Milanovic2018-08-081-3/+7
* | Use settings for json and pcfMiodrag Milanovic2018-08-082-15/+52
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-087-89/+732
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