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* Remove redundant code after hashlib movegatecat2021-06-021-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-7/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update placers to use new cluster APIsgatecat2021-05-061-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* arch_api: Outline of new cluster APIgatecat2021-05-061-0/+33
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-0/+7
| | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* docs/archapi: Typo fixesgatecat2021-02-241-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update archapi.md with latest signature.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-20/+5
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Update docs/archapi.mdgatecat2021-02-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-12/+4
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+7
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-121-1/+1
| | | | | | | | | | | | | | Fix assertion failure when opening the GUI on an arch without any decals. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-0/+6
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update docs with API changesD. Shah2021-02-081-21/+160
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-1/+9
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* docs: Update archapi.md with IdStringListD. Shah2021-02-021-12/+12
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-1/+4
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Make BELs/PIPs lowercase as bels/pips per review comment.Keith Rothman2021-02-021-19/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update documentation.Keith Rothman2021-02-021-21/+33
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement partitioning in placer_heap.Keith Rothman2021-02-021-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add archcheck for partition methods.Keith Rothman2021-02-021-3/+20
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Make some partition names consistent.Keith Rothman2021-02-021-3/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-4/+39
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Spelling fixesD. Shah2021-01-281-4/+4
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Remove wire alias APIDavid Shah2020-10-151-10/+1
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-1/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* docs: Document getRouteBoundingBoxDavid Shah2020-02-031-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-0/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-14/+20
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| * Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-3/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-20/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-7/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-3/+9
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Arch attrs APIClifford Wolf2018-08-141-0/+15
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add pip locationsClifford Wolf2018-08-091-5/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-6/+4
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| * docs: Update Arch API Cell Timing docsDavid Shah2018-08-081-6/+4
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-28/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Modify docEddie Hung2018-08-061-2/+2
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* API change: Use CellInfo* and NetInfo* as cell/net handles (archapi docs)Clifford Wolf2018-08-051-16/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update archapi.mdClifford Wolf2018-08-011-1/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve archapi docClifford Wolf2018-08-011-76/+263
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move FAQ, Wiki stuff to docs/Clifford Wolf2018-08-011-0/+282
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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