| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| * | | fix formating | Miodrag Milanovic | 2019-12-14 | 1 | -2/+1 | |
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| * | | more new wires added | Miodrag Milanovic | 2019-12-14 | 1 | -1/+10 | |
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| * | | ebr, mult and alu nice display | Miodrag Milanovic | 2019-12-14 | 1 | -1/+1 | |
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| * | | clangformat run | Miodrag Milanovic | 2019-12-08 | 1 | -27/+30 | |
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| * | | display IOs properly | Miodrag Milanovic | 2019-12-07 | 1 | -21/+5 | |
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| * | | More bels show properly | Miodrag Milanovic | 2019-12-07 | 1 | -43/+82 | |
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| * | | add dcca bels and dummy parts for other bels | Miodrag Milanovic | 2019-12-07 | 1 | -9/+54 | |
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| * | | more pips, and valid mapping | Miodrag Milanovic | 2019-11-10 | 1 | -4/+4 | |
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| * | | Draw some pips, fixed H6 and V6 | Miodrag Milanovic | 2019-11-09 | 1 | -1/+22 | |
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| * | | Show V02/V06/H02/H06 | Miodrag Milanovic | 2019-10-25 | 1 | -1/+1 | |
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| * | | Split graphics calls for wires into gfx.cc | Miodrag Milanovic | 2019-10-20 | 1 | -268/+3 | |
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| * | | muxes only together with slices | Miodrag Milanovic | 2019-10-20 | 1 | -9/+7 | |
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| * | | Remove not used line | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 | |
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| * | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 1 | -170/+114 | |
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| * | | fix slice wire | Miodrag Milanovic | 2019-10-20 | 1 | -20/+20 | |
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| * | | bound signals | Miodrag Milanovic | 2019-10-20 | 1 | -0/+65 | |
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| * | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 1 | -1/+37 | |
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| * | | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 1 | -176/+191 | |
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| * | | finixed slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+27 | |
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| * | | wd wires | Miodrag Milanovic | 2019-10-20 | 1 | -1/+21 | |
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| * | | Fix look of some wires | Miodrag Milanovic | 2019-10-20 | 1 | -6/+9 | |
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| * | | Add output wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+35 | |
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| * | | fix mux display | Miodrag Milanovic | 2019-10-20 | 1 | -2/+2 | |
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| * | | set wire active flag | Miodrag Milanovic | 2019-10-20 | 1 | -1/+1 | |
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| * | | clk and lsr muxes | Miodrag Milanovic | 2019-10-20 | 1 | -1/+62 | |
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| * | | draw rest of slice wires and more from switchbox | Miodrag Milanovic | 2019-10-20 | 1 | -3/+52 | |
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| * | | Optimize | Miodrag Milanovic | 2019-10-20 | 1 | -12/+4 | |
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| * | | Add other side of slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -9/+24 | |
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| * | | Display rest of slice input wires | Miodrag Milanovic | 2019-10-20 | 1 | -2/+8 | |
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| * | | Start adding visible wires | Miodrag Milanovic | 2019-10-20 | 1 | -1/+38 | |
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| * | | Draw swbox, smaller slices, proper io | Miodrag Milanovic | 2019-10-20 | 1 | -10/+113 | |
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| * | ecp5: Preparations for new IO bels | David Shah | 2019-10-09 | 1 | -0/+4 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | ecp5: Adding support for 36-bit wide PDP RAMs | David Shah | 2019-10-01 | 1 | -4/+17 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | ecp5: Add full part name to bitstream header | David Shah | 2019-08-27 | 1 | -0/+20 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | ecp5: Add GSR/SGSR support | David Shah | 2019-08-27 | 1 | -2/+6 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Merge pull request #309 from YosysHQ/dsptiming | David Shah | 2019-08-09 | 1 | -1/+17 | |
| |\ | | | | | ecp5: Conservative analysis of comb DSP timing | |||||
| | * | ecp5: Conservative analysis of comb DSP timing | David Shah | 2019-07-08 | 1 | -1/+17 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | ecp5: Add --out-of-context for building hard macros | David Shah | 2019-08-07 | 1 | -1/+7 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | ecp5: New Property interface | David Shah | 2019-08-05 | 1 | -2/+2 | |
| |/ | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Merge master | Miodrag Milanovic | 2019-06-25 | 1 | -3/+5 | |
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| | * | ecp5: Delay tweaking for lower speed grades | David Shah | 2019-06-21 | 1 | -2/+4 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | ecp5: Reduce cfg.criticalityExponent for now | David Shah | 2019-06-21 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Use flags for each step | Miodrag Milanovic | 2019-06-14 | 1 | -2/+2 | |
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| * | | Save top level attrs and store current step | Miodrag Milanovic | 2019-06-07 | 1 | -0/+2 | |
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| * | | Cleanup | Miodrag Milanovic | 2019-06-07 | 1 | -11/+0 | |
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| * | | No need for this one | Miodrag Milanovic | 2019-06-07 | 1 | -4/+0 | |
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| * | | ecp5: Use an attribute to store is_global | David Shah | 2019-06-07 | 1 | -1/+2 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | WIP saving/loading attributes | Miodrag Milanovic | 2019-06-07 | 1 | -0/+17 | |
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| * | Add --placer option and refactor placer selection | David Shah | 2019-03-24 | 1 | -9/+21 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | ecp5: Speedup cell delay lookups | David Shah | 2019-03-22 | 1 | -1/+7 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/nextpnr | |
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