aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/arch.cc
Commit message (Collapse)AuthorAgeFilesLines
...
* | draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-201-3/+52
| |
* | OptimizeMiodrag Milanovic2019-10-201-12/+4
| |
* | Add other side of slice wiresMiodrag Milanovic2019-10-201-9/+24
| |
* | Display rest of slice input wiresMiodrag Milanovic2019-10-201-2/+8
| |
* | Start adding visible wiresMiodrag Milanovic2019-10-201-1/+38
| |
* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-201-10/+113
|/
* ecp5: Preparations for new IO belsDavid Shah2019-10-091-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-4/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add full part name to bitstream headerDavid Shah2019-08-271-0/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #309 from YosysHQ/dsptimingDavid Shah2019-08-091-1/+17
|\ | | | | ecp5: Conservative analysis of comb DSP timing
| * ecp5: Conservative analysis of comb DSP timingDavid Shah2019-07-081-1/+17
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: New Property interfaceDavid Shah2019-08-051-2/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge masterMiodrag Milanovic2019-06-251-3/+5
|\
| * ecp5: Delay tweaking for lower speed gradesDavid Shah2019-06-211-2/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Reduce cfg.criticalityExponent for nowDavid Shah2019-06-211-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Use flags for each stepMiodrag Milanovic2019-06-141-2/+2
| |
* | Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+2
| |
* | CleanupMiodrag Milanovic2019-06-071-11/+0
| |
* | No need for this oneMiodrag Milanovic2019-06-071-4/+0
| |
* | ecp5: Use an attribute to store is_globalDavid Shah2019-06-071-1/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+17
|/
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-9/+21
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Speedup cell delay lookupsDavid Shah2019-03-221-1/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add PlacerHeapCfgDavid Shah2019-03-221-2/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Make HeAP placer optionalDavid Shah2019-03-221-1/+18
| | | | | | | | | | | | | A CMake option 'BUILD_HEAP' (default on) configures building of the HeAP placer and the associated Eigen3 dependency. Default for the iCE40 is SA placer, with --heap-placer to use HeAP Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for large ECP5 designs and HeAP tends to give better QoR. --sa-placer can be used to use SA instead, and auto-fallback to SA if HeAP not built. Signed-off-by: David Shah <dave@ds0.me>
* HeAP: tidying upDavid Shah2019-03-221-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Use for ECP5 as well as iCE40David Shah2019-03-221-7/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add TAUCS wrapper and integrationDavid Shah2019-03-221-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: DELAY fixesDavid Shah2019-02-251-5/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve packing densityDavid Shah2019-02-251-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add criticality-based LUT permutationDavid Shah2019-02-251-1/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Delay tuningDavid Shah2019-02-251-18/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix global clock routing with multiclock DPRAMDavid Shah2019-02-251-3/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router performance improvementsDavid Shah2019-02-251-4/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Implement budget overrides for carry chains and SLICE muxesDavid Shah2019-02-251-2/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve delay modelDavid Shah2019-02-251-3/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Speed up timing analysisDavid Shah2019-02-251-4/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ECLKSYNCB supportDavid Shah2019-02-241-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Packing of ODDRX2FDavid Shah2019-02-241-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Helper functions for DQS and ECLKDavid Shah2019-02-241-0/+37
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add timing data for DQS-related cellsDavid Shah2019-02-241-0/+27
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+22
|\
| * ecp5: Fix global routing performanceDavid Shah2019-02-121-1/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-091-1/+28
|/
* ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-081-0/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IOLOGIC timing and bitstream; ODDR workingDavid Shah2018-12-141-0/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding mux support up to LUT6David Shah2018-11-161-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 22:55:27 +0000