aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/bitstream.cc
Commit message (Collapse)AuthorAgeFilesLines
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-60/+55
|
* ecp5: accept lowercase characters in hex strings.Maya2022-03-111-1/+1
|
* ecp5: verify hex strings contain only valid characters.Maya2022-03-111-1/+6
|
* refactor: New member functions to replace design_utilsgatecat2022-02-181-15/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-273/+222
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: LUT permutation supportgatecat2021-12-131-3/+55
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-08-141-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Enable OPENDRAIN on differential outputsGreg Davill2021-08-141-1/+13
|
* ecp5: Add DCSC supportgatecat2021-07-061-0/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use new cluster APIgatecat2021-05-061-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
|
* Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
|
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-162/+162
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-10/+5
| | | | | | | This is a complete implementation of IdStringList for ECP5; excluding the GUI (which you will have to disable for it to build). Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Fix bottom clock tile renaming for tilegroupsD. Shah2021-01-251-0/+8
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* clangformatDavid Shah2020-12-301-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve pseudo-diff IO error handlingDavid Shah2020-12-271-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2020-11-141-4/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix handling of CLK/LSR wire attached settingsDavid Shah2020-11-051-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for setting PIO clampDavid Shah2020-09-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add SYSCONFIG settings to bitstreamDavid Shah2020-07-121-2/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2020-05-161-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
|
* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Handle OPENDRAIN attribute.Gary Wong2020-04-031-0/+3
|
* Enum/int compatibility for EHXPLLL parametersMartin2020-04-021-2/+7
| | | | | | - Lattice component EHXPLLL parameter compatibility, allowing to pass an int parameter for the enum (as expected by trellis tile) e.g. CLKOP_TRIM_DELAY : integer := 0;
* ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-4/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix differential inputsDavid Shah2020-03-081-1/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add SPICB0 IO supportDavid Shah2020-01-201-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for top pseudo diff outputsDavid Shah2020-01-151-12/+35
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for flipflops with preloadDavid Shah2019-12-071-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix 25k DDRDLLA bitstream genDavid Shah2019-11-291-2/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix dynamic DELAYF controlDavid Shah2019-11-181-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Allow setting drive strength for 3V3 IOsDavid Shah2019-10-261-0/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for IO registersDavid Shah2019-10-091-0/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Preparations for new IO belsDavid Shah2019-10-091-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-15/+22
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for clock gating with DCCADavid Shah2019-08-311-1/+29
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add full part name to bitstream headerDavid Shah2019-08-271-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-6/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: New Property interfaceDavid Shah2019-08-051-56/+75
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve error message for bad chars in BRAM init stringsDavid Shah2019-06-081-7/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Derived constraint support for PLLs, clock dividers and oscillatorsDavid Shah2019-02-241-3/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 03:10:53 +0000