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* | propagate w and hMiodrag Milanovic2019-12-141-60/+96
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* | pips for other type of connection boxMiodrag Milanovic2019-12-141-5/+17
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* | more new wires addedMiodrag Milanovic2019-12-145-2/+214
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* | ebr, mult and alu nice displayMiodrag Milanovic2019-12-142-8/+15
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* | add moreMiodrag Milanovic2019-12-133-4/+44
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* | new wires in dbMiodrag Milanovic2019-12-133-20/+498
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* | added siologicMiodrag Milanovic2019-12-134-2/+63
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* | Add many new wiresMiodrag Milanovic2019-12-134-0/+1250
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* | clangformat runMiodrag Milanovic2019-12-083-329/+364
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* | display IOs properlyMiodrag Milanovic2019-12-071-21/+5
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* | More bels show properlyMiodrag Milanovic2019-12-071-43/+82
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* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
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* | Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
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* | add more pipsMiodrag Milanovic2019-12-011-0/+49
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* | Handle H00 and V00Miodrag Milanovic2019-11-111-6/+49
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* | More pips and fix for V01Miodrag Milanovic2019-11-111-42/+170
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* | cleanupMiodrag Milanovic2019-11-111-174/+78
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* | proper h06 and v06Miodrag Milanovic2019-11-111-34/+39
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* | More pips addedMiodrag Milanovic2019-11-101-41/+200
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* | more pips, and valid mappingMiodrag Milanovic2019-11-102-10/+23
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* | Fixed V2, some more pipsMiodrag Milanovic2019-11-101-12/+43
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* | more pipsMiodrag Milanovic2019-11-101-2/+43
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* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-093-31/+58
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* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-253-13/+105
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* | display horizontal wires, add some globals to listMiodrag Milanovic2019-10-234-1/+123
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* | Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-203-268/+304
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* | type needs to be part of hash for GroupIdMiodrag Milanovic2019-10-201-1/+3
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* | muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
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* | Remove not used lineMiodrag Milanovic2019-10-201-2/+0
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* | Simplify layout of elementsMiodrag Milanovic2019-10-204-400/+254
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* | fix slice wireMiodrag Milanovic2019-10-201-20/+20
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* | bound signalsMiodrag Milanovic2019-10-201-0/+65
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* | more wires between switchboxesMiodrag Milanovic2019-10-204-2/+59
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* | Add more types of wiresMiodrag Milanovic2019-10-202-177/+221
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* | Less types neededMiodrag Milanovic2019-10-202-56/+24
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* | finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
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* | wd wiresMiodrag Milanovic2019-10-202-1/+32
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* | Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
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* | Add output wiresMiodrag Milanovic2019-10-201-0/+35
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* | fix mux displayMiodrag Milanovic2019-10-201-2/+2
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* | set wire active flagMiodrag Milanovic2019-10-202-1/+3
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* | clk and lsr muxesMiodrag Milanovic2019-10-202-1/+93
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* | draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-202-7/+106
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* | OptimizeMiodrag Milanovic2019-10-202-18/+87
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* | Add other side of slice wiresMiodrag Milanovic2019-10-202-14/+118
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* | Display rest of slice input wiresMiodrag Milanovic2019-10-202-3/+69
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* | Start adding visible wiresMiodrag Milanovic2019-10-205-10/+99
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* | Added type to wireMiodrag Milanovic2019-10-203-1/+87
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* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-204-28/+157
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* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
| | | | Signed-off-by: David Shah <dave@ds0.me>