Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | | display horizontal wires, add some globals to list | Miodrag Milanovic | 2019-10-23 | 4 | -1/+123 | |
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* | | Split graphics calls for wires into gfx.cc | Miodrag Milanovic | 2019-10-20 | 3 | -268/+304 | |
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* | | type needs to be part of hash for GroupId | Miodrag Milanovic | 2019-10-20 | 1 | -1/+3 | |
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* | | muxes only together with slices | Miodrag Milanovic | 2019-10-20 | 1 | -9/+7 | |
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* | | Remove not used line | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 | |
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* | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 4 | -400/+254 | |
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* | | fix slice wire | Miodrag Milanovic | 2019-10-20 | 1 | -20/+20 | |
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* | | bound signals | Miodrag Milanovic | 2019-10-20 | 1 | -0/+65 | |
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* | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 4 | -2/+59 | |
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* | | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 2 | -177/+221 | |
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* | | Less types needed | Miodrag Milanovic | 2019-10-20 | 2 | -56/+24 | |
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* | | finixed slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+27 | |
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* | | wd wires | Miodrag Milanovic | 2019-10-20 | 2 | -1/+32 | |
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* | | Fix look of some wires | Miodrag Milanovic | 2019-10-20 | 1 | -6/+9 | |
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* | | Add output wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+35 | |
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* | | fix mux display | Miodrag Milanovic | 2019-10-20 | 1 | -2/+2 | |
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* | | set wire active flag | Miodrag Milanovic | 2019-10-20 | 2 | -1/+3 | |
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* | | clk and lsr muxes | Miodrag Milanovic | 2019-10-20 | 2 | -1/+93 | |
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* | | draw rest of slice wires and more from switchbox | Miodrag Milanovic | 2019-10-20 | 2 | -7/+106 | |
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* | | Optimize | Miodrag Milanovic | 2019-10-20 | 2 | -18/+87 | |
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* | | Add other side of slice wires | Miodrag Milanovic | 2019-10-20 | 2 | -14/+118 | |
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* | | Display rest of slice input wires | Miodrag Milanovic | 2019-10-20 | 2 | -3/+69 | |
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* | | Start adding visible wires | Miodrag Milanovic | 2019-10-20 | 5 | -10/+99 | |
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* | | Added type to wire | Miodrag Milanovic | 2019-10-20 | 3 | -1/+87 | |
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* | | Draw swbox, smaller slices, proper io | Miodrag Milanovic | 2019-10-20 | 4 | -28/+157 | |
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* | ecp5: Add support for ECLKBRIDGECS | David Shah | 2019-10-11 | 1 | -1/+52 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Fix tristate IO registers | David Shah | 2019-10-09 | 1 | -3/+9 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Add support for IO registers | David Shah | 2019-10-09 | 2 | -0/+103 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Add IDDR71B support | David Shah | 2019-10-09 | 2 | -3/+16 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Add ODDR71B support | David Shah | 2019-10-09 | 1 | -3/+14 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Preparations for new IO bels | David Shah | 2019-10-09 | 3 | -1/+16 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Fix parameters | David Shah | 2019-10-04 | 1 | -0/+4 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Adding support for 36-bit wide PDP RAMs | David Shah | 2019-10-01 | 4 | -19/+96 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | Merge pull request #332 from YosysHQ/dave/python-refactor | David Shah | 2019-09-19 | 1 | -96/+2 | |
|\ | | | | | Improving Python API and adding docs for it | |||||
| * | python: Refactor out bindings shared between ECP5 and iCE40 | David Shah | 2019-09-15 | 1 | -96/+2 | |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into ↵ | David Shah | 2019-09-19 | 1 | -18/+31 | |
|\ \ | | | | | | | | | | xobs-precompiled-bba | |||||
| * | | ecp5: add support for PREGENERATED_BBA_PATH | Sean Cross | 2019-09-17 | 1 | -18/+31 | |
| |/ | | | | | | | | | | | | | Support pre-generated bba files to speed up compiling on Windows and get it compiling on Darwin. Signed-off-by: Sean Cross <sean@xobs.io> | |||||
* | | Merge pull request #330 from zeldin/bba | David Shah | 2019-09-19 | 1 | -5/+6 | |
|\ \ | |/ |/| | bba: Default to native endian in bbasm | |||||
| * | CMake: Generate chipdbs in build tree when building out-of-tree | Marcus Comstedt | 2019-09-15 | 1 | -3/+4 | |
| | | | | | | | | Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> | |||||
| * | bba: Require explicit endianness flag, and supply it | Marcus Comstedt | 2019-09-15 | 1 | -2/+2 | |
| | | | | | | | | Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> | |||||
* | | python: Fix getWireBelPins | David Shah | 2019-09-15 | 2 | -0/+20 | |
|/ | | | | | | Fixes #327 Signed-off-by: David Shah <dave@ds0.me> | |||||
* | Merge pull request #329 from YosysHQ/dave/net_aliases | David Shah | 2019-09-13 | 1 | -0/+5 | |
|\ | | | | | json: Add support for net aliases | |||||
| * | json: Add support for net aliases | David Shah | 2019-09-13 | 1 | -0/+5 | |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | | ecp5: Move clock constraints across IO and DCCA | David Shah | 2019-09-13 | 1 | -0/+9 | |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: use $PYTHON_EXECUTABLE for python path | Sean Cross | 2019-09-09 | 1 | -2/+2 | |
| | | | | | | | | Sometimes the python executable might have a different name. Cmake sets the $PYTHON_EXECUTABLE variable to point to the binary path, so use this variable. Signed-off-by: Sean Cross <sean@xobs.io> | |||||
* | ecp5: Add support for clock gating with DCCA | David Shah | 2019-08-31 | 2 | -39/+87 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Add full part name to bitstream header | David Shah | 2019-08-27 | 3 | -0/+23 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | ecp5: Add GSR/SGSR support | David Shah | 2019-08-27 | 4 | -3/+22 | |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
* | Rename clock restriction attribute to "noglobal" | Arnaud Durand | 2019-08-24 | 1 | -2/+2 | |
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* | Restrict clock promotion to global | Arnaud Durand | 2019-08-22 | 1 | -0/+3 | |
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