aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5
Commit message (Collapse)AuthorAgeFilesLines
* proper h06 and v06Miodrag Milanovic2019-11-111-34/+39
|
* More pips addedMiodrag Milanovic2019-11-101-41/+200
|
* more pips, and valid mappingMiodrag Milanovic2019-11-102-10/+23
|
* Fixed V2, some more pipsMiodrag Milanovic2019-11-101-12/+43
|
* more pipsMiodrag Milanovic2019-11-101-2/+43
|
* Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-093-31/+58
|
* Show V02/V06/H02/H06Miodrag Milanovic2019-10-253-13/+105
|
* display horizontal wires, add some globals to listMiodrag Milanovic2019-10-234-1/+123
|
* Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-203-268/+304
|
* type needs to be part of hash for GroupIdMiodrag Milanovic2019-10-201-1/+3
|
* muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
|
* Remove not used lineMiodrag Milanovic2019-10-201-2/+0
|
* Simplify layout of elementsMiodrag Milanovic2019-10-204-400/+254
|
* fix slice wireMiodrag Milanovic2019-10-201-20/+20
|
* bound signalsMiodrag Milanovic2019-10-201-0/+65
|
* more wires between switchboxesMiodrag Milanovic2019-10-204-2/+59
|
* Add more types of wiresMiodrag Milanovic2019-10-202-177/+221
|
* Less types neededMiodrag Milanovic2019-10-202-56/+24
|
* finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
|
* wd wiresMiodrag Milanovic2019-10-202-1/+32
|
* Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
|
* Add output wiresMiodrag Milanovic2019-10-201-0/+35
|
* fix mux displayMiodrag Milanovic2019-10-201-2/+2
|
* set wire active flagMiodrag Milanovic2019-10-202-1/+3
|
* clk and lsr muxesMiodrag Milanovic2019-10-202-1/+93
|
* draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-202-7/+106
|
* OptimizeMiodrag Milanovic2019-10-202-18/+87
|
* Add other side of slice wiresMiodrag Milanovic2019-10-202-14/+118
|
* Display rest of slice input wiresMiodrag Milanovic2019-10-202-3/+69
|
* Start adding visible wiresMiodrag Milanovic2019-10-205-10/+99
|
* Added type to wireMiodrag Milanovic2019-10-203-1/+87
|
* Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-204-28/+157
|
* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for IO registersDavid Shah2019-10-092-0/+103
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IDDR71B supportDavid Shah2019-10-092-3/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Preparations for new IO belsDavid Shah2019-10-093-1/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-014-19/+96
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #332 from YosysHQ/dave/python-refactorDavid Shah2019-09-191-96/+2
|\ | | | | Improving Python API and adding docs for it
| * python: Refactor out bindings shared between ECP5 and iCE40David Shah2019-09-151-96/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into ↵David Shah2019-09-191-18/+31
|\ \ | | | | | | | | | xobs-precompiled-bba
| * | ecp5: add support for PREGENERATED_BBA_PATHSean Cross2019-09-171-18/+31
| |/ | | | | | | | | | | | | Support pre-generated bba files to speed up compiling on Windows and get it compiling on Darwin. Signed-off-by: Sean Cross <sean@xobs.io>
* | Merge pull request #330 from zeldin/bbaDavid Shah2019-09-191-5/+6
|\ \ | |/ |/| bba: Default to native endian in bbasm
| * CMake: Generate chipdbs in build tree when building out-of-treeMarcus Comstedt2019-09-151-3/+4
| | | | | | | | Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
| * bba: Require explicit endianness flag, and supply itMarcus Comstedt2019-09-151-2/+2
| | | | | | | | Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
* | python: Fix getWireBelPinsDavid Shah2019-09-152-0/+20
|/ | | | | | Fixes #327 Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #329 from YosysHQ/dave/net_aliasesDavid Shah2019-09-131-0/+5
|\ | | | | json: Add support for net aliases
| * json: Add support for net aliasesDavid Shah2019-09-131-0/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-15 19:10:56 +0000