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* clangformatgatecat2022-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0712-1348/+1136
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* ecp5: Fix double-counting of FFs in reportgatecat2022-03-161-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: accept lowercase characters in hex strings.Maya2022-03-111-1/+1
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* ecp5: verify hex strings contain only valid characters.Maya2022-03-111-1/+6
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* Merge pull request #925 from YosysHQ/gatecat/netlist-ivgatecat2022-03-013-46/+39
|\ | | | | Switch to potentially-sparse net users array
| * Switch to potentially-sparse net users arraygatecat2022-02-273-46/+39
| | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Fix PDPW16K clock param renaminggatecat2022-02-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-185-238/+238
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-1611-1318/+1674
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-85/+79
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-163-63/+36
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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-14/+9
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: LUT permutation supportgatecat2021-12-137-7/+117
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-132-14/+15
| | | | This reduces the final binary size by ~7 MB for 85k
* clangformatgatecat2021-12-121-4/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use a vector rather than dictMatt Johnston2021-12-123-14/+106
| | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix mistype.YRabbit2021-09-291-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-08-241-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #798 from kleinai/extref-locgatecat2021-08-191-6/+44
|\ | | | | Make EXTREFB handling more robust
| * Make EXTREFB handling more robustAidan Klein2021-08-181-6/+44
| | | | | | | | | | Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA. Also adds location constraints specifically for EXTREFB.
* | clangformatgatecat2021-08-141-2/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Enable OPENDRAIN on differential outputsGreg Davill2021-08-141-1/+13
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* ecp5: Copy REGMODE in PDP mode to both A and B portsgatecat2021-08-021-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Add DCSC supportgatecat2021-07-064-11/+55
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-1221-27/+27
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Don't attempt to promote undriven nets to globalsgatecat2021-06-071-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove redundant code after hashlib movegatecat2021-06-021-70/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-027-49/+33
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in placersgatecat2021-06-021-9/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-026-81/+80
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use new cluster APIgatecat2021-05-063-20/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-301-40/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
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* Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible.
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
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* Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
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* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-153-10/+21
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* timing: Replace all users of criticality with new enginegatecat2021-03-041-9/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix compiler warnings introduced by -Wextragatecat2021-02-252-2/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-86/+48
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-164-58/+32
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 03:52:36 +0000