| Commit message (Collapse) | Author | Age | Files | Lines |
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specify one.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
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interchange: Add caching of site LUT mapping solution
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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same net
Signed-off-by: gatecat <gatecat@ds0.me>
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interchange: Fix handling of constants in macros
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Changes:
- Adds LUT output pin to LutBelPOD.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Previous code allowed router to entire sites with no sinks.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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- Add IDEMPOTENT_CHECK define to perform some expected idempotent
operations more than once to verify they work as expected.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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[FPGA interchange] Convert some string constants to IdString.
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Also add some optional diagnostic prints for cell -> BEL pin mapping.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Currently the lookahead is disabled by default because of the time to
compute and RAM usage. However it does appear to work reasonably well
in testing. Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Refine site router
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The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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