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* Added fallback to VCC as the preferred constant if the architecture does not ↵Maciej Kurc2022-05-121-1/+12
| | | | | | specify one. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-111-7/+36
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-041-0/+9
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Switch to potentially-sparse net users arraygatecat2022-02-271-2/+2
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-3/+5
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-221-0/+11
|\ | | | | interchange: Add caching of site LUT mapping solution
| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-221-4/+6
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added more code comments, formatted the codeMaciej Kurc2021-07-221-2/+4
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Working site LUT mapping cacheMaciej Kurc2021-07-161-0/+7
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | interchange: add constraints constraints application routineAlessandro Comodi2021-07-121-0/+1
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Allow pseudo pip wires to overlap with bound site wires on the ↵gatecat2021-07-061-8/+3
| | | | | | same net Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
|\ | | | | interchange: Fix handling of constants in macros
| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-011-0/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-0/+1
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Using hashlib in archesgatecat2021-06-021-16/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Preliminary implementation of macro expansiongatecat2021-05-211-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Run clangformatgatecat2021-05-161-2/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-131-11/+15
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
| | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Adding a basic global buffer placergatecat2021-05-071-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Initial global routing implementationgatecat2021-05-071-0/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-0/+53
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-121-9/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
| | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-6/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-0/+11
| | | | | | | Previous pseudo pips were the same cost as regular pips, but this is definitely too fast, and meant that the router was prefering them. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-5/+22
| | | | | | | This prevents the general router from routing through sites, which is not legal in FPGA interchange. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-4/+35
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-011-1/+6
| | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
| | | | | | Previous code allowed router to entire sites with no sinks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+30
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-98/+35
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fixup some of the re-mapping logic.Keith Rothman2021-03-251-24/+74
| | | | | | | - Add IDEMPOTENT_CHECK define to perform some expected idempotent operations more than once to verify they work as expected. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-20/+95
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-4/+25
|\ | | | | [FPGA interchange] Convert some string constants to IdString.
| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-4/+25
| | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Initial version of inverter logic.Keith Rothman2021-03-231-0/+31
| | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-231-41/+5
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial lookahead for FPGA interchange.Keith Rothman2021-03-231-13/+39
| | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #637 from litghost/refine_site_routergatecat2021-03-221-2/+30
|\ | | | | Refine site router
| * Rework FPGA interchange site router.Keith Rothman2021-03-221-2/+30
| | | | | | | | | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-2/+2
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 04:55:49 +0000