| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Use physical placement from device DB
It should reduce runtime
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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interchange: Add caching of site LUT mapping solution
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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same net
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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If get_net_type was called before the driver was placed, it could return
the wrong value.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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[FPGA interchange] Add support for global buffers from chipdb.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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[FPGA interchange] Convert some string constants to IdString.
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Also add some optional diagnostic prints for cell -> BEL pin mapping.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Currently the lookahead is disabled by default because of the time to
compute and RAM usage. However it does appear to work reasonably well
in testing. Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Refine site router
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The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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