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path: root/fpga_interchange/archdefs.h
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* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-21/+0
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-0/+4
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move all string data into BBA file.Keith Rothman2021-02-051-18/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update copywrite headers.Keith Rothman2021-02-041-1/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-041-5/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+22
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+189
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>