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path: root/fpga_interchange/fpga_interchange.cpp
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* interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-1/+5
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Using hashlib in archesgatecat2021-06-021-34/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-6/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-7/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Correct some bugs in writing of physical netlist w.r.t. site sources.Keith Rothman2021-03-221-11/+93
| | | | | | | Local site sources should have their driving BEL pin included in the net so that the site wire is driven by an output BEL pin. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-11/+41
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-2/+11
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-21/+34
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial working constant network support!Keith Rothman2021-02-231-9/+106
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix sign mismatch.Keith Rothman2021-02-181-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Emit fixed attributes to output physical netlist.Keith Rothman2021-02-171-8/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-171-10/+49
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Small fixes from review.Keith Rothman2021-02-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-0/+826
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 15:29:58 +0000