iCE40/nextpnr - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Using hashlib in arches	gatecat	2021-06-02	1	-7/+7
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	clangformat	gatecat	2021-04-12	1	-7/+4
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	[interchange] Prevent site router from generating incorrect LUTs.	Keith Rothman	2021-04-06	1	-6/+12
\| \| \| \| \| \| \| \| \|	The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	[interchange] Add crude pseudo pip model.	Keith Rothman	2021-04-06	1	-1/+41
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Add some FIXME's around VCC assumption in LUT logic.	Keith Rothman	2021-03-25	1	-0/+17
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Re-work LUT mapping logic to only put VCC pins when required.	Keith Rothman	2021-03-25	1	-5/+111
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Refactor header structures in FPGA interchange Arch.	Keith Rothman	2021-03-19	1	-1/+17
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Use NEXTPNR_NAMESPACE macro's now that headers are seperated.	Keith Rothman	2021-03-15	1	-1/+1
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	clangformat	gatecat	2021-03-03	1	-92/+86
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Initial LUT rotation logic.	Keith Rothman	2021-02-26	1	-0/+370
	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>