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* LUT mapping ceche optimizations 2Maciej Kurc2021-07-161-80/+0
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Working site LUT mapping cacheMaciej Kurc2021-07-161-15/+92
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Using hashlib in archesgatecat2021-06-021-7/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-121-7/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-061-6/+12
| | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-1/+41
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-5/+111
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-1/+17
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-03-031-92/+86
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Initial LUT rotation logic.Keith Rothman2021-02-261-0/+370
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-23 00:14:27 +0000