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* Switch to potentially-sparse net users arraygatecat2022-02-274-7/+8
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* okami: new Viaduct archLofty2022-02-247-1/+638
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* refactor: New member functions to replace design_utilsgatecat2022-02-185-20/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-15/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-11/+5
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* viaduct: Allow constraining only cascades without fanoutgatecat2022-02-042-2/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add missing Pip vector bindinggatecat2022-02-042-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Viaduct API for a hybrid between generic and full-custom archgatecat2022-01-0418-28/+1055
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Refactor for faster performancegatecat2021-12-306-205/+319
| | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-5/+6
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-129-11/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-025-36/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-023-16/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-222-0/+7
| | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-6/+20
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-232-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-60/+31
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Don't generate Vcc if not neededgatecat2021-02-171-5/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-162-16/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add APIs for controlling cell->bel pin mappinggatecat2021-02-154-3/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-152-0/+4
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-102-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-114-8/+12
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* generic: Base upon ArchAPID. Shah2021-02-051-102/+132
| | | | | | | As generic is often picked as our 'odd-one-out' we also use it as an example of an Arch that does not build upon BaseArch. Signed-off-by: D. Shah <dave@ds0.me>
* generic: Fix pin names accidentally being IdStringList not IdStringD. Shah2021-02-052-4/+4
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-043-23/+19
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Post-rebase fixD. Shah2021-02-021-4/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* generic: Use IdStringList for all arch object namesD. Shah2021-02-024-107/+118
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-022-39/+25
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pybindings for new APIs.Keith Rothman2021-02-021-0/+26
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-022-10/+10
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish implementing new generic APIs.Keith Rothman2021-02-021-3/+15
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add archcheck for partition methods.Keith Rothman2021-02-022-0/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove wire alias APIDavid Shah2020-10-153-26/+2
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* Update generic synth script for dfflegalize changesPepijn de Vos2020-09-181-0/+1
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* clangformatMiodrag Milanovic2020-07-251-26/+26
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* proper argument propagationMiodrag Milanovic2020-07-241-26/+28
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* Initial conversion to pybind11Miodrag Milanovic2020-07-231-35/+35
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* Fix spelling of 'unsupported'Nathaniel Graff2020-05-131-1/+1
| | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
* Merge pull request #391 from YosysHQ/router2-upstreamDavid Shah2020-02-042-2/+44
|\ | | | | Upstreaming router2
| * generic: Implement getRouteBoundingBoxDavid Shah2020-02-032-0/+26
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Allow selection of router algorithmDavid Shah2020-02-032-2/+18
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #385 from YosysHQ/router1-arc-fixesDavid Shah2020-02-031-1/+2
|\ \ | |/ |/| Fixes for partial reconfig demo
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