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* gowin: Use local aliasesYRabbit2022-06-091-7/+11
| | | | | | | | | | | | | | | | | | In the Gowin chips, the tiles are connected to each other by a one-hop wire, among others. There are 4 one-hop wires, of which 2 are shared between north/south and east/west, have three names: e.g. SN10 and N110 and S110. But only one of them, the first, occurs as a sink for PIP, that is, you can not get a route that would pass through the S110 for example. This commit corrects the names to SN?0 and EW?0 at the wire creation stage to avoid dead wires. In addition, the SN?0 and EW?0 are among the few sinks for global clock wires and now there is the possibility of a more optimal clock routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for long wiresYRabbit2022-05-271-4/+202
| | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
| | | | | | | Only the recognition of the directive in the .CST file and elementary checks are added, but not the long-wire mechanism itself. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: handle the GW1N-9 feature.YRabbit2022-04-031-2/+17
| | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix z-index of oscillatorTim Pambor2022-03-301-4/+4
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* gowin: Add bels for oscillatorTim Pambor2022-03-271-0/+38
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* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-261-0/+15
| | | | | | | The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Name the constants (#958)YRabbit2022-03-211-2/+2
| | | | | Place arbitrary constants side by side to avoid conflicts. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: use global VCC and VSS nets (#956)Pepijn de Vos2022-03-191-1/+10
| | | | | | | * use global VCC and VSS nets * derp * remove init parameter
* gowin: add support for ODDR primitiveYRabbit2022-03-151-1/+52
| | | | | | | | | Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add the Global Set/Reset primitiveYRabbit2022-03-121-0/+8
| | | | | | | | | GSR is added automatically if it was not instantiated by the user explicitly. Compatible with old apicula bases, the functionality does not work, but the crash does not happen --- just a warning. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: BUGFIX gui crashYRabbit2022-03-041-0/+10
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: New member functions to replace design_utilsgatecat2022-02-181-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-12/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Remove leftover debuggingYRabbit2022-02-041-1/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into diff-locationsYRabbit2022-02-041-9/+223
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| * gowin: Add GUI.YRabbit2022-01-291-9/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add a DS location recognitionYRabbit2022-02-031-12/+18
|/ | | | | | | | | For differential signals it is necessary to set the position of two pins at once: P and N. This commit adds that capability and also adds another style of location setting --- with the pin letter in square brackets used in vendor tools. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix last MUX8YRabbit2022-01-031-1/+1
| | | | | | In fact, there is also an input/output column. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add simplified IO cells processingYRabbit2021-12-201-0/+33
| | | | | | | | | | | | | | | Some models have I/O cells that are IOBUFs, and other types (IBUFs and OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done with general-purpose routing so it's best to do it here to avoid conflicts. For this purpose, in the new bases, these special cells are of type IOBS (IOB Simplified). The proposed changes are compatible with bases of previous versions of Apycula and do not require changing .CST constraint files. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-4/+5
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Fix spelling of messagesYRabbit2021-12-141-4/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Check the chipdb versionYRabbit2021-11-071-1/+5
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Use speed from chip base.YRabbit2021-11-051-14/+25
| | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-041-4/+19
| | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
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* gowin: Replace the zero delays with reasonable values.YRabbit2021-10-091-12/+35
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for wide LUTs.YRabbit2021-10-071-8/+100
| | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Place DFFs of different types in the slice.YRabbit2021-08-311-2/+26
| | | | | | | | | | | | | | | | | Allow the registers of the same type or pairs shown below to be placed in the same slide: |--------|--------| | DFFS | DFFR | | DFFSE | DFFRE | | DFFP | DFFC | | DFFPE | DFFCE | | DFFNS | DFFNR | | DFFNSE | DFFNRE | | DFFNP | DFFNC | | DFFNPE | DFFNCE | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add constraints on primitive placement.YRabbit2021-08-311-11/+32
| | | | | | | | | | Added support for the INS_LOC instruction in the constraints file (.CST), which is used to specify object placement. Expanded treatment of IO_LOC/IO_PORT constraints, which now can be applied to both ports and IO buffers. Port constraints have priority. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add the IO[TRBL]style placement recognitionYRabbit2021-08-231-5/+37
| | | | | | | | | Specifying pin placement with this notation (e.g. IOR4B) allows to use the same constraint file without changes for different packages and even different families. The vendor router also understands this notation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Change the constraint parser to support multiple options per line. ↵YRabbit2021-08-061-6/+11
| | | | | | Add support for IOBUF and TBUF I/O modes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fix the boolean.YRabbit2021-07-081-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fix formatingYRabbit2021-07-071-24/+24
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fix boolean value.YRabbit2021-07-071-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Wip parserYRabbit2021-07-071-16/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* ParserYRabbit2021-07-051-0/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fix parser. Comments and IO_PORTYRabbit2021-07-031-11/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* SyntaxYRabbit2021-07-021-3/+3
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Add IO_PORT parsingYRabbit2021-07-021-14/+27
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* only one type of dff per slicePepijn de Vos2021-02-281-1/+7
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* Fix compiler warnings introduced by -Wextragatecat2021-02-251-16/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-33/+23
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Fix archcheck errors and add to CIgatecat2021-02-171-1/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Fix IdStrings being overwritten by wireToGlobalgatecat2021-02-171-8/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-15/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+2
| | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
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