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* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-2/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Let the placer know about global networksYRabbit2022-07-041-257/+229
| | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-241-7/+8
| | | | | | Also removed the useless references. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a separate router for the clocksYRabbit2022-06-231-0/+335
A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>