aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/arch.cc
Commit message (Collapse)AuthorAgeFilesLines
* timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing_opt: Make an optional pass controlled by command lineDavid Shah2018-12-061-3/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-12-061-3/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+4
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
| | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-0/+2
| | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-191-0/+19
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-4/+4
|\
| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-131-4/+4
| |
* | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-18/+62
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
|\ | | | | Resolve issue #72
| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
| |
* | clangformatDavid Shah2018-09-301-1/+0
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Validity check for LVDS IODavid Shah2018-09-241-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Remove obsolete belType memberDavid Shah2018-09-241-1/+0
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-191-0/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-191-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-3/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-11/+2
|\ | | | | Use settings for placer1 and router1
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-11/+2
| |
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-2/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-0/+33
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-22/+77
|\
| * ice40: Add error for unknown cell type when getting timing infoDavid Shah2018-08-081-1/+3
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Add timing arcs through global buffersDavid Shah2018-08-081-0/+4
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * timing: Debugging implementation of new timing APIDavid Shah2018-08-081-1/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * ice40: Timing arch fixDavid Shah2018-08-081-3/+17
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * timing: Update to new use API (currently broken)David Shah2018-08-081-2/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * Arch API: New specification for timing port classesDavid Shah2018-08-081-18/+50
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * clangformatEddie Hung2018-08-061-10/+12
| |
| * Merge branch 'master' into assign_budget_speedupEddie Hung2018-08-061-2/+17
| |\
| * | Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+5
| | |
* | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-43/+20
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-110/+20
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40's getBudgetOverride() to return correct delay for different devicesEddie Hung2018-08-061-2/+17
|/
* Fix ice40's getBudgetOverride() to override only for COUT -> CINEddie Hung2018-08-061-1/+1
|
* Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-4/+6
|
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-08-051-34/+32
|
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-58/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add generation of models to tmfuzzClifford Wolf2018-08-041-0/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-16/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-1/+6
|\
| * clangformatDavid Shah2018-08-041-1/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 20:59:57 +0000