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* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Implement getRouteBoundingBox for router2David Shah2020-02-031-0/+24
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-2/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Make HeAP the default placerDavid Shah2019-11-261-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Major Property improvements for common and iCE40David Shah2019-08-051-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformat runMiodrag Milanovic2019-06-251-2/+3
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* Merge masterMiodrag Milanovic2019-06-251-0/+8
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| * ice40: add RGB_DRV/LED_DRV_CUR support for u4kSimon Schubert2019-06-101-0/+8
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* | Use flags for each stepMiodrag Milanovic2019-06-141-2/+2
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* | Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+2
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* | CleanupMiodrag Milanovic2019-06-071-11/+0
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* | WIP saving/loading attributesMiodrag Milanovic2019-06-071-4/+20
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* ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrsSylvain Munaut2019-04-171-2/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-0/+21
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-2/+13
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add PlacerHeapCfgDavid Shah2019-03-221-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Make HeAP placer optionalDavid Shah2019-03-221-4/+7
| | | | | | | | | | | | | A CMake option 'BUILD_HEAP' (default on) configures building of the HeAP placer and the associated Eigen3 dependency. Default for the iCE40 is SA placer, with --heap-placer to use HeAP Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for large ECP5 designs and HeAP tends to give better QoR. --sa-placer can be used to use SA instead, and auto-fallback to SA if HeAP not built. Signed-off-by: David Shah <dave@ds0.me>
* HeAP: Add TAUCS wrapper and integrationDavid Shah2019-03-221-2/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix u4k in external chipdb mode.Marcin Kościelnicki2019-03-191-3/+3
| | | | Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
* ice40: support u4kSimon Schubert2019-02-231-2/+12
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* ice40: Fix timing class of 'padin' GB outputsDavid Shah2019-02-201-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Load chipdb from filesystem as optionMiodrag Milanovic2019-02-091-1/+30
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* Merge pull request #220 from YosysHQ/coi3Eddie Hung2019-01-291-6/+9
|\ | | | | ice40: Add budget override for CO->I3 path
| * [ice40] Refactor Arch::getBudgetOverride()Eddie Hung2019-01-291-29/+9
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| * ice40: Add budget override for CO->I3 pathDavid Shah2019-01-271-0/+23
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Path related fixesDavid Shah2019-01-271-5/+29
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add timing data for all IO modesDavid Shah2019-01-071-3/+65
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing_opt: Make an optional pass controlled by command lineDavid Shah2018-12-061-3/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-12-061-3/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+4
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
| | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-0/+2
| | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-191-0/+19
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-4/+4
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-131-4/+4
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* | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-18/+62
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
|\ | | | | Resolve issue #72
| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
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* | clangformatDavid Shah2018-09-301-1/+0
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Validity check for LVDS IODavid Shah2018-09-241-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: Remove obsolete belType memberDavid Shah2018-09-241-1/+0
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-191-0/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-191-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-3/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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