Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ice40: Add support for SB_RGBA_DRV | Sylvain Munaut | 2018-11-19 | 1 | -0/+4 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add support for SB_GB_IO | Sylvain Munaut | 2018-11-19 | 1 | -0/+1 |
| | | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Introduce the concept of forPadIn SB_GB | Sylvain Munaut | 2018-11-19 | 1 | -0/+2 |
| | | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/arch: Add helper to check if a BEL is LOCKED or not | Sylvain Munaut | 2018-11-19 | 1 | -0/+19 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 1 | -4/+4 |
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| * | [ice40] getBudgetOverride() to use constrained Z not placed Z | Eddie Hung | 2018-11-13 | 1 | -4/+4 |
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* | | timing: Fix handling of clock inputs | David Shah | 2018-11-12 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Working on multi-clock analysis | David Shah | 2018-11-12 | 1 | -6/+4 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | timing: iCE40 Arch API changes for clocking info | David Shah | 2018-11-12 | 1 | -18/+62 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #88 from YosysHQ/issue72 | Eddie Hung | 2018-10-11 | 1 | -6/+13 |
|\ | | | | | Resolve issue #72 | ||||
| * | [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE | Eddie Hung | 2018-09-15 | 1 | -6/+13 |
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* | | clangformat | David Shah | 2018-09-30 | 1 | -1/+0 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | ice40: Validity check for LVDS IO | David Shah | 2018-09-24 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | ice40: Remove obsolete belType member | David Shah | 2018-09-24 | 1 | -1/+0 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Add more missing iCE40 gfx (LP/HX is complete now) | Clifford Wolf | 2018-08-19 | 1 | -0/+46 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add iCE40 gfx for IO span-4 corners | Clifford Wolf | 2018-08-19 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add iCE40 gfx for span-4 wires between IO tiles | Clifford Wolf | 2018-08-19 | 1 | -3/+9 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #47 from YosysHQ/settings_propagate | Clifford Wolf | 2018-08-18 | 1 | -11/+2 |
|\ | | | | | Use settings for placer1 and router1 | ||||
| * | Use settings for placer1 and router1 | Miodrag Milanovic | 2018-08-09 | 1 | -11/+2 |
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* | | Improve iCE40 gfx for IO tiles and RAM tiles | Clifford Wolf | 2018-08-18 | 1 | -2/+6 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add ice40 wire attributes (grid position, segment list) | Clifford Wolf | 2018-08-18 | 1 | -0/+33 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge branch 'master' of github.com:YosysHQ/nextpnr into constids | Clifford Wolf | 2018-08-08 | 1 | -22/+77 |
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| * | ice40: Add error for unknown cell type when getting timing info | David Shah | 2018-08-08 | 1 | -1/+3 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | Arch API: Removing Arch::isIOCell | David Shah | 2018-08-08 | 1 | -2/+0 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | ice40: Add timing arcs through global buffers | David Shah | 2018-08-08 | 1 | -0/+4 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | timing: Debugging implementation of new timing API | David Shah | 2018-08-08 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | ice40: Timing arch fix | David Shah | 2018-08-08 | 1 | -3/+17 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | timing: Update to new use API (currently broken) | David Shah | 2018-08-08 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | Arch API: New specification for timing port classes | David Shah | 2018-08-08 | 1 | -18/+50 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | clangformat | Eddie Hung | 2018-08-06 | 1 | -10/+12 |
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| * | Merge branch 'master' into assign_budget_speedup | Eddie Hung | 2018-08-06 | 1 | -2/+17 |
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| * | | Add new Arch::isIOCell() API function | Eddie Hung | 2018-08-06 | 1 | -0/+5 |
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* | | | Get rid of old iCE40 id_ Arch members | Clifford Wolf | 2018-08-08 | 1 | -43/+20 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Get rid of PortPin and BelType (ice40, generic, docs) | Clifford Wolf | 2018-08-08 | 1 | -110/+20 |
| |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | ice40's getBudgetOverride() to return correct delay for different devices | Eddie Hung | 2018-08-06 | 1 | -2/+17 |
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* | Fix ice40's getBudgetOverride() to override only for COUT -> CIN | Eddie Hung | 2018-08-06 | 1 | -1/+1 |
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* | Change getBudgetOverride() signature to return bool and modify budget in place | Eddie Hung | 2018-08-06 | 1 | -4/+6 |
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* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) | Clifford Wolf | 2018-08-05 | 1 | -3/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | clangformat | Clifford Wolf | 2018-08-05 | 1 | -34/+32 |
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* | Add new iCE40 delay estimator and delay predictor | Clifford Wolf | 2018-08-04 | 1 | -58/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add generation of models to tmfuzz | Clifford Wolf | 2018-08-04 | 1 | -0/+30 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Refactor ice40 timing fuzzer used to create delay estimates | Clifford Wolf | 2018-08-04 | 1 | -16/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm | Clifford Wolf | 2018-08-04 | 1 | -1/+6 |
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| * | clangformat | David Shah | 2018-08-04 | 1 | -1/+2 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | Add constraint weight as a command line option | David Shah | 2018-08-03 | 1 | -1/+5 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Proper ice40 wire types | Clifford Wolf | 2018-08-03 | 1 | -0/+39 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 pseudo-pips for lut permutation | Clifford Wolf | 2018-08-03 | 1 | -2/+15 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | ice40: Use real cell timings | David Shah | 2018-08-02 | 1 | -22/+17 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Add Router1Cfg | Clifford Wolf | 2018-08-02 | 1 | -1/+5 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Remove getFrameDecal() API | Clifford Wolf | 2018-08-01 | 1 | -12/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> |