aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/pack.cc
Commit message (Collapse)AuthorAgeFilesLines
* Fixing old emails and names in copyrightsgatecat2021-06-121-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-10/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-31/+34
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-7/+7
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* ice40: Use snake case for arch-specific functionsD. Shah2021-02-031-6/+6
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-021-14/+14
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-021-5/+4
| | | | | | This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Switch from RelPtr to RelSliceD. Shah2021-01-271-8/+5
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Nicer error for unconstrained SB_GB_IODavid Shah2020-12-271-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Clarify feedback paths in PLL constraints codeDavid Shah2020-12-031-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Derive PLL timing constraintsDavid Shah2020-12-031-31/+138
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is usedSylvain Munaut2020-11-101-7/+9
| | | | | | | | It's been confirmed that : (1) this is required by the hardware (2) icecube will force that field to 4'b1111 in fixed mode Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: If IO is used by SB_GB_IO, can't use it for PLLSylvain Munaut2020-07-091-1/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Derive oscillator frequency constraintsDavid Shah2020-03-291-0/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Always copy DFF attrs to LCDavid Shah2020-03-191-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Preserve hierarchy through packingDavid Shah2019-12-271-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* frontend/generic: Fix regressionsDavid Shah2019-12-271-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Preserve top level IO properlyDavid Shah2019-10-191-13/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for PLL DELAY_ADJUSTMENT_MODEDavid Shah2019-09-231-1/+15
| | | | | | Fixes #336 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Move clock constraints across SB_IO and SB_GB_IODavid Shah2019-09-131-0/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add better stats on LC packingDavid Shah2019-08-081-1/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix regressionDavid Shah2019-08-051-1/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Major Property improvements for common and iCE40David Shah2019-08-051-29/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformat runMiodrag Milanovic2019-06-251-17/+15
|
* Merge masterMiodrag Milanovic2019-06-251-4/+33
|\
| * clangformatDavid Shah2019-06-241-3/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ice40: add RGB_DRV/LED_DRV_CUR support for u4kSimon Schubert2019-06-101-4/+31
| |
* | Use flags for each stepMiodrag Milanovic2019-06-141-1/+1
| |
* | Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+1
| |
* | Add vcc and gnd nets and cells only if neededMiodrag Milanovic2019-06-071-5/+20
| |
* | WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+1
| |
* | Revert "Do not add VCC if not used, loading json works"Miodrag Milanovic2019-06-021-6/+5
| | | | | | | | This reverts commit f1b3a14bc23ccee6acaf6bbe27827523dc13c111.
* | Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
| |
* | Do not add VCC if not used, loading json worksMiodrag Milanovic2019-05-311-5/+6
|/
* ice40: Add support for HFOSC trimmingSylvain Munaut2019-05-131-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Only create padin gbuf for PLLs if global output actually usedSylvain Munaut2019-04-171-11/+38
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Take placed SB_GBs into account when placing PLLsSylvain Munaut2019-04-161-9/+55
| | | | | | | | | | | | | | | | Because the PLLs drive global networks, we need to account for already existing and placed SB_GBs when trying to place/pack them. Theses can be user instanciated SB_GBs with BEL attribute, or SB_GB_IOs that got converted during the IO packing. This patch assumes that: - If a PLL is used the output A global network is always used, even if there is no connection to the global output pin - If a PLL with a singe output is used, then the B output global network is still free to be used by whatever. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/pack: During IO packing, remove any unused input connectionSylvain Munaut2019-04-111-0/+13
| | | | | | | | | This is mostly for the benefit of PLL placement because the D_IN_x ports are used for other purposes when PLL is enabled so we need to make sure nothing is connected there already. (even an unused net is too much) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Don't constrain to a PLL bel that has already been usedDavid Shah2019-04-011-0/+2
| | | | | | Fixes #258 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-1/+18
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
|\ | | | | ice40/pack: Copy attributes to packed cell
| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
| | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
|/ | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Improve handling of unconstrained IODavid Shah2018-12-261-3/+0
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
|
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 00:43:01 +0000