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* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-192-84/+73
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-195-2/+53
* ice40/chipdb: Add wires to global network for all cells that can drive itSylvain Munaut2018-11-193-6/+22
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-192-37/+63
* ice40: Fix BEL validity check for PLL vs SB_IOSylvain Munaut2018-11-191-21/+20
* ice40: Improve the is_sb_pll40_XXX predicates collectionSylvain Munaut2018-11-191-1/+13
* ice40: Fix PLLTYPE for SB_PLL40_2F_PADSylvain Munaut2018-11-191-1/+1
* ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
* ice40: Make PLL default FEEDBACK_MODE to SIMPLESylvain Munaut2018-11-191-1/+1
* ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
* ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
* ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-192-0/+21
* ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
* clangformatDavid Shah2018-11-161-2/+2
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-132-4/+5
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-132-4/+5
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-133-18/+41
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-132-17/+40
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| | * Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+3
| | * clangformatClifford Wolf2018-11-111-4/+1
| | * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-14/+29
| | * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-9/+17
| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
* | | timing: Add support for clock constraintsDavid Shah2018-11-122-0/+12
* | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+6
* | | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
* | | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-123-21/+68
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* | ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
* | Merge pull request #93 from YosysHQ/gui_changesMiodrag Milanović2018-11-101-2/+2
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| * fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
* | ice40: Fix SPRAM and IO globalsDavid Shah2018-11-041-0/+4
* | ice40: Fix PLL DYNAMICDELAYDavid Shah2018-10-271-1/+2
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* ups, uncommentMiodrag Milanovic2018-10-271-2/+2
* Fixed pip graphicsMiodrag Milanovic2018-10-271-4/+4
* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
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| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
* | Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
* | ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
* | Refactor chain finder to its own fileDavid Shah2018-09-301-39/+1
* | clangformatDavid Shah2018-09-308-28/+34
* | Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-258-13/+88
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| * | ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
| * | ice40: Tristate IO support fixesDavid Shah2018-09-243-6/+10
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