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| * timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
* | ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
* | ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
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* clangformatDavid Shah2018-12-062-2/+3
* ice40: Put debug logging behind ctx->debugDavid Shah2018-12-061-3/+5
* ice40: Fix carry chain splittingDavid Shah2018-12-051-1/+1
* ice40: Don't split carry chain in simple feed-out casesDavid Shah2018-12-041-7/+50
* ice40: Include I3 connectivity in chainDavid Shah2018-12-041-23/+25
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-015-1/+26
* ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
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| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
* | ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
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| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
* | ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
* | ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
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* ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
* ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
* ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-262-2/+8
* ice40: Improve PCF error handlingDavid Shah2018-11-261-3/+9
* Merge branch 'master' of github.com:YosysHQ/nextpnrDavid Shah2018-11-261-0/+2
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| * ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
* | python: Fixes to get net wires map workingDavid Shah2018-11-221-2/+24
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* ice40/pll: Fix typo when testing for global port output netSylvain Munaut2018-11-201-1/+1
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-195-2/+58
* ice40: Add global network output support for LFOSC/HFOSCSylvain Munaut2018-11-191-2/+10
* ice40/pack: Add helper to constain cells that are unique in the FPGASylvain Munaut2018-11-191-0/+16
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-195-8/+31
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-192-84/+73
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-195-2/+53
* ice40/chipdb: Add wires to global network for all cells that can drive itSylvain Munaut2018-11-193-6/+22
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-192-37/+63
* ice40: Fix BEL validity check for PLL vs SB_IOSylvain Munaut2018-11-191-21/+20
* ice40: Improve the is_sb_pll40_XXX predicates collectionSylvain Munaut2018-11-191-1/+13
* ice40: Fix PLLTYPE for SB_PLL40_2F_PADSylvain Munaut2018-11-191-1/+1
* ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
* ice40: Make PLL default FEEDBACK_MODE to SIMPLESylvain Munaut2018-11-191-1/+1
* ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
* ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
* ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-192-0/+21
* ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
* clangformatDavid Shah2018-11-161-2/+2
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