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* Use unified io location dataMiodrag Milanovic2023-03-201-12/+2
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* Use TRELLIS primitivesMiodrag Milanovic2023-03-208-40/+39
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* Use RelSlice, make more in line with ecp5 archMiodrag Milanovic2023-03-204-146/+113
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* cmake: Make HeAP placer always-enabledgatecat2023-03-172-11/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-03-174-24/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix out of tree builds and place h in generatedMiodrag Milanovic2023-03-163-3/+3
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* Let top tiles be on topMiodrag Milanovic2023-03-161-3/+3
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* Enable wires and add dummy wire type for nowMiodrag Milanovic2023-03-164-7/+32
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* Basic GUI part selectionMiodrag Milanovic2023-03-162-3/+3
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* Fix examplesMiodrag Milanovic2023-03-165-6/+6
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* Extend chipdb with metadataMiodrag Milanovic2023-03-1610-202/+189
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* add new field handling in chip config formatMiodrag Milanovic2023-03-162-0/+4
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* Add simple BEL graphicsMiodrag Milanovic2023-03-165-1/+245
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* Expand list of possible devicesMiodrag Milanovic2023-03-162-4/+29
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* machxo2: Fix Python bindings for pip iteratorsLofty2023-02-131-2/+2
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* Add missing <set> includesgatecat2023-01-202-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-211-2/+2
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* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Switch to potentially-sparse net users arraygatecat2022-02-271-1/+1
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-182-10/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-167-64/+81
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-72/+59
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-16/+9
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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-7/+8
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* clangformat.William D. Jones2021-12-162-9/+12
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* machxo2: Remove no-iobs option. It was always enabled and should remain an ↵William D. Jones2021-12-166-8/+5
| | | | implementation detail.
* machxo2: Remove -noiopad option when generating miters for post-pnr ↵William D. Jones2021-12-161-1/+2
| | | | verification.
* machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports.William D. Jones2021-12-161-0/+46
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* machxo2: Correct which PIO wires get adjusted when writing text bitstream. ↵William D. Jones2021-12-161-9/+26
| | | | Add verbose logging for adjustments.
* machxo2: Fix packing for directly-connected DFFs.William D. Jones2021-07-013-9/+28
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* machxo2: Add VHDL primitives, demo, and script.William D. Jones2021-07-014-0/+81
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* machxo2: Add a special case for pips whose config bits are in multipleWilliam D. Jones2021-07-011-0/+12
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* machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.William D. Jones2021-07-011-2/+17
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* machxo2: Set Pip and Wire delays to reasonable fake values mirroringWilliam D. Jones2021-07-011-2/+2
| | | | estimateDelay.
* Fixing old emails and names in copyrightsgatecat2021-06-1213-15/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove redundant code after hashlib movegatecat2021-06-021-43/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-024-9/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-023-17/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-061-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add same fix as in issue #373Miodrag Milanovic2021-04-081-0/+4
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* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-7/+18
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-253-15/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-192-36/+3
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-163-12/+1
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Misc tidying upgatecat2021-02-122-8/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Python bindings and stub GUIgatecat2021-02-125-6/+188
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
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