Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | mistral: clean up bel init slightly | Lofty | 2021-10-08 | 1 | -18/+6 |
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* | mistral: Adding support for MLABs as memory | gatecat | 2021-10-05 | 8 | -21/+235 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Add bel pins for MLAB write port | gatecat | 2021-10-03 | 2 | -19/+38 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | clangformat | gatecat | 2021-08-26 | 1 | -3/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Permute MLAB init bits correctly | gatecat | 2021-08-24 | 1 | -0/+22 |
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* | mistral: Use MLABs as if they're LABs (for now) | Lofty | 2021-08-17 | 4 | -50/+63 |
| | | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com> | ||||
* | mistral: Include mistral generated files in include dirs | gatecat | 2021-08-15 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix pip binding check | gatecat | 2021-08-14 | 1 | -4/+11 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Fixing old emails and names in copyrights | gatecat | 2021-06-12 | 2 | -2/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Remove mistral root argument | gatecat | 2021-06-04 | 3 | -7/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Build libmistral as a cmake subdir | gatecat | 2021-06-04 | 1 | -4/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Remove redundant code after hashlib move | gatecat | 2021-06-02 | 1 | -29/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Use hashlib in most remaining code | gatecat | 2021-06-02 | 1 | -2/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Using hashlib in arches | gatecat | 2021-06-02 | 5 | -20/+19 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Use hashlib for core netlist structures | gatecat | 2021-06-02 | 4 | -25/+25 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Add hash() member functions | gatecat | 2021-06-02 | 1 | -0/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix nextpnr build with LLVM | gatecat | 2021-06-02 | 3 | -4/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Make RBF compression optional | gatecat | 2021-05-30 | 2 | -1/+9 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: add getChipName | Lofty | 2021-05-15 | 1 | -1/+1 |
| | | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com> | ||||
* | mistral: Add MISTRAL_CLKBUF cell type | gatecat | 2021-05-15 | 5 | -1/+15 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Tidying up | gatecat | 2021-05-15 | 10 | -10/+10 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Make router2 the default | gatecat | 2021-05-15 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Speed up bel binding and checking | gatecat | 2021-05-15 | 1 | -4/+18 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Workaround for weird SCLR issue | gatecat | 2021-05-15 | 1 | -0/+7 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix ENA and ACLR bitstream generation | gatecat | 2021-05-15 | 4 | -4/+11 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Disable global buffers that are currently broken | gatecat | 2021-05-15 | 1 | -0/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Compensate for EF_SEL mirroring in validity check | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix EF_SEL and BTO_DIS | gatecat | 2021-05-15 | 2 | -4/+5 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: PKREG bits appear to be mirrored within a half? | gatecat | 2021-05-15 | 1 | -2/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Debugging flipflops | gatecat | 2021-05-15 | 1 | -3/+4 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Trim SDATA if SLOAD is low | gatecat | 2021-05-15 | 1 | -0/+9 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: FF&CLKBUF fixes, part 1 | gatecat | 2021-05-15 | 2 | -1/+10 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: First pass at FF and CLKBUF bitgen | gatecat | 2021-05-15 | 2 | -18/+115 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Account for TD input count limit | gatecat | 2021-05-15 | 4 | -9/+128 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | msitral: Fix pip iterator Python bindings | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Implement PIP locations, too | gatecat | 2021-05-15 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Implement bounding boxes for router2 | gatecat | 2021-05-15 | 2 | -1/+15 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Debugging carry chain issues | gatecat | 2021-05-15 | 2 | -13/+34 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Adding FF control set reservation | gatecat | 2021-05-15 | 3 | -58/+148 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Carry fixes | gatecat | 2021-05-15 | 2 | -3/+16 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Carry debugging | gatecat | 2021-05-15 | 3 | -41/+11 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Write arith mode to bitstream (not yet functional) | gatecat | 2021-05-15 | 2 | -2/+18 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: First pass at carry packing | gatecat | 2021-05-15 | 4 | -8/+82 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: FF validity checking fixes | gatecat | 2021-05-15 | 1 | -7/+13 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix constant trimming | gatecat | 2021-05-15 | 2 | -1/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Write LUT inits | gatecat | 2021-05-15 | 2 | -1/+72 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Add some IO configuration | gatecat | 2021-05-15 | 1 | -0/+30 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Setting some more boilerplate bits | gatecat | 2021-05-15 | 3 | -1/+118 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Add stub RBF generation | gatecat | 2021-05-15 | 4 | -9/+108 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Rename clock buffer primitive | gatecat | 2021-05-15 | 2 | -2/+3 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> |